This thesis attacks two important issues in back end of an optimizing compiler: instruction selection and register allocation.
这篇论文尝试解决优化编译器的后端中的两个重要的问题：指令选择和寄存器分配。
We also present optimization in instruction scheduling and register allocation phase for this ASIP architecture.
并在指令调度和寄存器分配阶段针对这种ASIP处理器的结构做了优化。
Register allocation and instruction scheduling are two important tasks for every optimizing compiler.
寄存器分配与指令调度是编译器优化过程中的两项重要任务。
Register allocation and instruction scheduling are two important tasks for every optimizing compiler.
寄存器分配与指令调度是编译器优化过程中的两项重要任务。
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