With this multiplier adder unit, we can implement FIR filters with any orders.
采用该乘加单元我们可以实现任何阶数高速FIR滤波器。
This paper presents a new high speed FIR Filter structure which includes a unique multiplier adder unit.
本文提出了一种新型的高速滤波器结构，此结构的核心是一种独特的乘加单元。
The circuits of asynchronous adder unit, asynchronous comparator unit, and asynchronous selector unit are proposed.
给出了一种异步实现结构的异步加法单元、异步比较单元和异步选择单元电路。
The arithmetic logic unit(ALU) decides the performance of the Central Processing Unit(CPU), while the adder decides that of the ALU.
算术逻辑运算单元（ALU）决定着中央处理器（CPU）的性能，而加法器又决定着ALU的性能。
The arithmetic logic unit(ALU) decides the performance of the Central Processing Unit(CPU), while the adder decides that of the ALU.
算术逻辑运算单元（ALU）决定着中央处理器（CPU）的性能，而加法器又决定着ALU的性能。
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