Often an adder bite goes unnoticed or is confused with an insect sting until the ensuing pain gets the victim’s attention.
如果被蝰蛇咬了一口，人们经常会误以为只是蚊虫叮咬，直到接踵而来的剧痛，受害者才会明白过来。
An adder, a snake, was in Old English “a nadder”; and an auger, the thing you dig holes for fence posts with, was “a nauger”.
an adder（蝰蛇）在古英语中写作anadder；anauger（你用来挖洞放置栅栏的钻子）原先写作anauger。
The hognose snake，sometimes called the puff adder，is one of nature's clowns．Some people think that he is deadly poisonous．Actually，he's just a harmless fellow who spends most of his time huntingtoads．
猪鼻蛇，有时也被称作膨身蛇，是自然界丑角中的一员。 有人认为它是剧毒蛇，其实，它恰恰是无害的，其大部分时间用于捕捉蟾蜍。
Thou shalt tread upon the lion and adder: the young lion and the dragon shalt thou trample under feet.
你要踹在狮子和虺蛇的身上，践踏少壮狮子和大蛇。
Floating-point adder is one of the basic parts of CPU. Its performance has a direct effect on CPU floating-point processing capacity.
浮点加法器是构成CPU的基本部件之一，其性能优劣将直接影响CPU浮点处理能力。
一条小毒蛇攻击了我父亲。
The adder is Britain's only venomous snake.
蝰蛇是英国唯一的一种毒蛇。
High-speed digit-serial adder and its application.
高速数字串行加法器及其应用。
This adder can realize the optical arithmetic operation with two inputs.
该加法器可以实现两输入的光学算术运算。
A 32-bit sparse tree adder with modified carry tree structure is proposed.
提出了一种改进进位运算的32位稀疏树加法器。
The carry skip adder optimal block sizes can minimize critical path delay.
优化方块分配的进位跳跃加法器可以缩短关键路径的延时。
Integer adder, shifter and LZA these key parts are mainly studied and optimally designed.
着重研究了整数加法器、移位器、先导零预测逻辑等浮点加法器关键部件的优化设计。
QSERL 4 bit carry ripple adder (RCA) is designed and compared with static CMOS counterpart.
设计了4位QSERL串行进位加法器(RCA)电路，和相应的CMOS电路进行了功耗比较。
Disclosed is a safety explosion proof type sodium hydride adder which is an integral structure.
安全防爆型氢化钠添加器，是一个整体结构。
It is called "half-adder" because it has only two inputs and does not provide for a carry input.
它之所以称为半加器是因为它只有两个输入，即没有进位输入。
This CCA USES only 17 multiplexers, whereas a classic conditional sum adder USES 28 multiplexers.
这个CCA装置只用了17个多工器，而一个传统的条件和加法器要用28个多工器。
The ideas presented in this paper are then demonstrated on the design of an ECL 1-bit full adder.
所提出的方法已用一位全加器的设计实例予以演示。
It shows that mirrored adder is better than carry look ahead adder in arithmetic speed and layout.
结果表明镜像加法器在运算速度、版图布局上都优于超前进位加法器。
The adder adds the first electric power with the second electric power to gain a third electric power.
该加法器用于将该第一电功率与该第二电功率相加以得到一第三电功率。
The adder (250) adds a pixel value of the image and the output of the feedback computing section (240).
加法器(250)将图像的像素值与反馈计算部分(240)的输出相加。
This paper presents a new high speed FIR Filter structure which includes a unique multiplier adder unit.
本文提出了一种新型的高速滤波器结构，此结构的核心是一种独特的乘加单元。
The concept used is that the bits of the two numbers to be added are made available to the adder synchronously.
所用的方法是，将相加两数的各位同步地输入到加法器中。
To accelerate the adder, a new parallel integer addition algorithm - carry barrel adder algorithm was proposed.
为了提高加法器的运算速度，提出了一种新型并行整数加法算法——桶形整数加法算法。
This paper brings forward a new viewpoint of using balanced ternary half-adder in the ternary optical computer.
提出了在三值光计算机中采用对称三进制半加器的观点，设计了支持这个观点的半加器结构原理图。
A digital adder needs more circuitry, and thus more power, to operate, but it does not require such high accuracy.
数字加法器需要更多的电路、因而需要更大的功率才能工作，但它不需要这么高的准确性。
The circuits of asynchronous adder unit, asynchronous comparator unit, and asynchronous selector unit are proposed.
给出了一种异步实现结构的异步加法单元、异步比较单元和异步选择单元电路。
A logic element designed to act as either an adder or a subtracter in accordance with the control signal applied to it.
根据供给它的控制信号，或起加法器作用或起减法器作用的一种逻辑元件。
The feedback computing section (240) filters the quantization error and outputs the result of the filtering to the adder (250).
反馈计算部分(240)将量化误差进行滤波，并且将滤波结果输出到加法器(250)。
A computer is comprised of some logic parts which have serial logic functions, and the adder is one of the combine logic circuits.
电子计算机是由具有各种逻辑功能的逻辑部件组成的，加法器就属于其中的组合逻辑电路。
Through the structure and logical designing, we get a high-speed and effective LOD circuit, which applied in floating-point adder.
我们从LOD的组成结构和逻辑两个方面进行设计，实现了一种快速、高效的LOD电路。
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