A monolithic microcomputer applied to medical color TV set realtime-data adder is described. It can be used to add and display data automatically and in realtime.
本文介绍了一种用单片机组成的医用彩色电视实时数据添加器，能对数据实时、自动地进行添加、显示。
(3) How do you specify that you want the info of, say, an indexer setter, or a property getter, or an event handler adder?
(3)你怎样指出你想要关于，比如说，一个索引设置者，一个属性获取者，或是一个事件处理添加者的信息呢？
Adder venom attacks the blood and nervous system.The venom of an adder bite is less toxic than that of a puff-adder, but it is far more toxic when injected intravenously.
蝰蛇毒素会破坏血液和神经系统，虽然蝰蛇一吻的毒性不如蝮蛇这么恐怖，但如果将毒素注射进皮肤，那毒性就大了去了。
A digital adder needs more circuitry, and thus more power, to operate, but it does not require such high accuracy.
数字加法器需要更多的电路、因而需要更大的功率才能工作，但它不需要这么高的准确性。
Using binary notation, 26 movable bit levers inside each bit serial adder convert the swing from the pendulum into a visible notation on the clock.
使用二进制表示法，在每个26位串行加法器动产位的杠杆转换成一个钟摆在摆动的时钟可见符号。
This paper proposes a new method, which USES the 4-2 compressor and CLA instead of the traditional adder to improve the transformation speed.
采用一种新颖的实现方法，利用4 - 2压缩器和超前进位加法器来代替传统的加法，提高了运算速度。
The hognose snake，sometimes called the puff adder，is one of nature's clowns．Some people think that he is deadly poisonous．Actually，he's just a harmless fellow who spends most of his time huntingtoads．
猪鼻蛇，有时也被称作膨身蛇，是自然界丑角中的一员。 有人认为它是剧毒蛇，其实，它恰恰是无害的，其大部分时间用于捕捉蟾蜍。
An adder, a snake, was in Old English “a nadder”; and an auger, the thing you dig holes for fence posts with, was “a nauger”.
an adder（蝰蛇）在古英语中写作anadder；anauger（你用来挖洞放置栅栏的钻子）原先写作anauger。
The bit serial adder system was chosen over a normal gear system because of the number of gears it takes to make the clock's calculations.
该位串行加法器系统是选择了一个由于齿轮数齿轮系统的正常需要，使时钟的计算。
A real time optical logic processor is presented, that can perform binary logic operations in parallel. Experimental result is given of the system as a half adder.
本文提出了一种能实时完成二进制逻辑运算的光学并行处理系统，并给出了作为半加法器的实验结果。
A computer is comprised of some logic parts which have serial logic functions, and the adder is one of the combine logic circuits.
电子计算机是由具有各种逻辑功能的逻辑部件组成的，加法器就属于其中的组合逻辑电路。
In order to deal with the significant digits addition we designed three inputs adder tree, and give a simple performance discuss of this method.
针对有效数相加问题，本文提出了三输入加法树的设计方法，并就其性能作了简要的分析。
Floating-point adder is one of the basic parts of CPU. Its performance has a direct effect on CPU floating-point processing capacity.
浮点加法器是构成CPU的基本部件之一，其性能优劣将直接影响CPU浮点处理能力。
A new type of optimal block distribution algorithm of two level carry-skip adder was described to determine optimal block distribution sizes.
提出了一种新的获得二级进位跳跃加法器优化方块分配的算法。
A self-test scheme, under which all test patterns for adder under test in VLSI are produced by the adder self, is presented based on arithmetic additive generator.
基于算术加法测试生成，提出了VLSI中加法器的一种自测试方案：加法器产生自身所需的所有测试矢量。
Another possibility is that the death worm is a member of the cobra family called the death adder.
另一种可能性是死亡蠕虫属于眼镜蛇家族的一员，叫做小蝰蛇。
Frequency controlled data (m) plus an accumulative phase data output by a phase register in an N-bit adder when a clock pulse comes, the result is sent to the input port of the phase register.
每来一个时钟脉冲，N位加法器将频率控制数据m与相位寄存器输出的累加相位数据相加，并将结果送相位寄存器输入端。
A logic element designed to act as either an adder or a subtracter in accordance with the control signal applied to it.
根据供给它的控制信号，或起加法器作用或起减法器作用的一种逻辑元件。
A 2-word 2-bit adder has been fabricated using conventional MOS technology. Design considerations and experimental results are...
文中给出了用常规的MOS工艺制造二位加法器的设计原理与实验结果。
A 2-word 2-bit adder has been fabricated using conventional MOS technology. Design considerations and experimental results are also given.
文中给出了用常规的MOS工艺制造二位加法器的设计原理与实验结果。
The authors have succeeded in devising a1024bit circular adder and it has been used in the circuit of RSA cryptosystem with a good effect.
笔者现已成功地设计了1024位循环式加法器，并应用到RSA密码体系的硬件电路中，得到了较好的效果。
To accelerate the adder, a new parallel integer addition algorithm - carry barrel adder algorithm was proposed.
为了提高加法器的运算速度，提出了一种新型并行整数加法算法——桶形整数加法算法。
A 32-bit sparse tree adder with modified carry tree structure is proposed.
提出了一种改进进位运算的32位稀疏树加法器。
It is called "half-adder" because it has only two inputs and does not provide for a carry input.
它之所以称为半加器是因为它只有两个输入，即没有进位输入。
This paper presents a new high speed FIR Filter structure which includes a unique multiplier adder unit.
本文提出了一种新型的高速滤波器结构，此结构的核心是一种独特的乘加单元。
In this paper, we present a polarization-encoded optical full adder by using an inverse vector realized by transmissive feedback.
提出了利用反转矢量透射反馈算法研制偏振编码光电混合全加器。
Through the structure and logical designing, we get a high-speed and effective LOD circuit, which applied in floating-point adder.
我们从LOD的组成结构和逻辑两个方面进行设计，实现了一种快速、高效的LOD电路。
A model of algorithm has been proposed for composite neural network and the classification results of high precision are obtained through a full adder (FA) fostered by the model.
提出了一种复合神经网络的算法模型，用该模型训练全加器(FA)获得了高精度分类结果。
This paper brings forward a new viewpoint of using balanced ternary half-adder in the ternary optical computer.
提出了在三值光计算机中采用对称三进制半加器的观点，设计了支持这个观点的半加器结构原理图。
This paper brings forward a new viewpoint of using balanced ternary half-adder in the ternary optical computer.
提出了在三值光计算机中采用对称三进制半加器的观点，设计了支持这个观点的半加器结构原理图。
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