该方法实现译码器的标准单元化设计，并且有效提高译码的速度，简化硬件设计。
The implementation carries out the standard-cell design of RS decoder, improves the velocity of decoding efficiently and simplifies the hard - ware design.
基于CPLD设计了一种能实现该种转换的HDB3码编译码器。
Based on the CPLD, a circuit of HDB3 CODEC is designed in this article to realize this transform.
接着介绍了R S码的编码原理和时域迭代译码算法，在此基础上设计实现RS码编码器和译码器。
Then, the code theory and time-domain iterative decode algorithm of RS code is introduced, RS coder and decoder are designed and implemented in this base.
所实现的编译码器能对BCH(23,12)码进行正确地编码和译码，能纠正小于或等于3位的随机错误。
The encoder can correctly encode and decode the BCH (23, 12) code which can correct less than or equal to 3 bit error.
本论文给出了一种简单分组码-（7，4）汉明码编、译码器的单片机实现方案。
This paper provides a hardware-realizing scheme of coding and decoding of(7,4) Hamming Code using the single chip microcomputer.
随着LDPC译码算法领域的研究日趋成熟和越来越易于硬件实现的发展趋势，LDPC译码器的VLSI实现才逐渐成为研究者关注的焦点。
With the development of LDPC algorithm which has a hardware-friendly trend, the VLSI realization of LDPC decoder is becoming ever the focus of researchers.
分析了HDB3译码器的原理，提出了一种基于FPGA技术的HDB3译码器的快速实现方法。
The principle of HDB3 decoder is analyzed. A quick way to implement HDB3 decoder based on FPGA is proposed.
利用准循环ldpc码的结构特点，使用半并行结构的译码器可以实现复杂度和译码速率的有效折中。
According to the structure of Quasi-Cyclic LDPC code, we can make a trade-off between hardware complexity and decoding throughput by applying semi-parallel architecture.
本论文内容来源于某通信设备研制项目，该项目中的“CRC-RS译码器的设计”要求采用RS和扩展缩短CRC码来实现。
The paper items from a project on developing communication devices. The implementation of CRC-RS decoder in the project asks for an adoption of RS and extended shortened CRC codes.
目前越来越多的通信系统采用LDPC码作为纠错码，这种硬件结构对其它系统的LDPC译码器设计及实现有一定的借鉴意义。
At present, more and more communication system use LDPC code as the channel coding scheme, the architecture in this paper will give a reference to design and implementation of other LDPC decoder.
指令译码器将编码指令信号进行译码，最后由驱动电路来驱动执行电路实现各种指令的操作。
Encoding instruction decoder for decoding command signals, and finally by the drive circuit to drive the implementation of circuit operation to achieve a variety of commands.
程序的主要功能是利用哈夫曼编码对数据进行无损压缩，实现Huffman压缩的编码器和译码器。
The main functions of the procedure is to use Huffman coding lossless compression of data to achieve Huffman compression encoder and decoder.
讨论了仿真系统的译码器、基于特征的加工数据库、实体建模以及仿真驱动等组成模块实现的关键技术和方法。
The overall architecture of the system consisted of code interpreter, modeling module, feature database of turning based on STEP-NC and simulation drive is established.
用FPGA设计并实现了标准中码长16200，码率2/3IRA码的编码器，且设计出相应的译码器结构。
The encoder of length 16200 and rate 2/3 IRA codes is designed and implemented with FPGA, and the corresponding decoder structure is designed.
目前对莫尔斯信号的译码器的研究都是针对单一信号源，信息传到PC机以后才能实现网络化传输。
Now the study of Morse signal decode is aimed at single signal source. The information can be transmitted in networks only after it is sent to PC.
硬件实现结果表明，该译码器的资源利用率远远超过了传统的单码率译码器。
Hardware implementation results show that the resource efficiency of the multi-rate decoder is much better than that of traditional single-rate decoders.
在达到设计要求的基础上本文对RS译码器做了进一步的研究，利用一种新型的复用流水线结构实现了多路RS译码器，有效的减少了每路译码所占用的资源。
In more research, a new multiplex pipeline is presented and is used to design multi-channel RS decoder. The proposed scheme greatly reduce resources per channel.
在达到设计要求的基础上本文对RS译码器做了进一步的研究，利用一种新型的复用流水线结构实现了多路RS译码器，有效的减少了每路译码所占用的资源。
In more research, a new multiplex pipeline is presented and is used to design multi-channel RS decoder. The proposed scheme greatly reduce resources per channel.
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