第三章详细阐述了压阻式加速度传感器的制作工艺，包括芯片工艺和盖板工艺。
The structure and dimension of the sensor were designed in this chapter. In chapter 3, the process of sensors is elaborated, the sensing element and cover board .
这项生产工艺将大大降低生产芯片的成本，而且拥有更快的速度和更强的功能以及更低的能耗。
The new production technology will enable the company to lower chip costs and power consumption, while adding more speed and functionality.
多晶硅常用在被称作门的晶体管元件中，已在标准的芯片制造工艺中使用了几十年。
Typically used in the transistor element called the gate, polysilicon has been part of the standard chip-manufacturing process for decades.
虽然实验室里已经造出了原型芯片，但它们采用的特殊材料很难被整合到当今的芯片制造工艺中。
Though prototype chips with optical-communications systems have been built in the lab, they rely on exotic materials that are difficult to integrate into existing chip-manufacturing processes.
英特尔希望在未来的几年里升级制作工艺，最终设计出更好的Atom芯片。
Intel hopes to eventually design better Atom chips in the coming years through upgraded manufacturing methods.
据该论文所述，该工艺过程可以生产的芯片间距只有6纳米。
According to the paper, the procedure can produce chips with gaps as small as 6 nanometers.
怀特赛兹教授的“纸芯片”相对于其他“芯片级实验室”方案来说要更加简便，其他的方案大多需要复杂的生产工艺并使用了诸如玻璃、塑料那样笨重的材料。
Whitesides' paper chips are much simpler than other lab-on-chip projects, many of which require intricate production methods and heavier materials such as glass and plastic.
目前最先进的芯片制造工艺为30纳米，这意味着芯片元件的平均尺寸为300亿分之一米。
The current state of the art for chip manufacturing is 30 nanometers, which means the average size of a chip component is just 30 billionths of a meter across.
图7所示为带状引线连接芯片和管壳装配的工艺程序。
Figure 7 shows the sequence for tape bonding the chip and assembling the package.
在制作上，根据性能和结构要求，采用了高密度布线、多芯片组装的薄膜工艺。
For fabrication, a thin film process of high density routing and multi-chip assembly is adopted to meet the performance and structure requirements.
Intel 22nm制程的工艺代号为1270，首批采用22nm制程技术制作的芯片将由设在俄勒冈州的D1D芯片厂负责制造，而今年下半年晚些时候，这款产品的量产则会在位于亚利桑那的F32工厂开始量产。
The 22-nm process is called 1270 and it is starting to ramp. First wafers will come out of D1D in Oregon and then volume production will start at F32 in Arizona in the later half of this year.
今天，一款45纳米工艺的芯片-Penryn，由英特尔公司推出，该芯片拥有82亿个晶体管。
Today, a 45-nanometer Penryn chip from Intel holds 820 million transistors.
这些芯片SRAM存储器通常用来获取新的芯片制造工艺调试。
These chips were SRAM memory chips often used to get new manufacturing processes debugged.
两者都是在一个单独的芯片是45纳米制造的，而仍然在CPU已经死了，是在新的32纳米工艺生产。
Both are on a separate die that is still manufactured in 45nm whereas the CPU die is already manufactured in the new 32nm process.
随着半导体工艺的进步，芯片集成度和运算速度的提高，互连寄生效应的影响也日益明显。
The influence of parasitic interconnect capacitance is much in evidence with the progress of the semiconductor techniques and the increase of chip density and calculated speed.
对一种先进的双悬臂梁高量程MEMS加速度计的单芯片封装工艺进行了失效机理分析。
Failure analysis is conducted for the single chip packaging process of an advanced high-range MEMS accelerometer with double cantilever beams.
随着生产工艺的提高，芯片上能集成越来越多的晶体管，多线程技术也逐步成为一种主流的处理器体系结构技术。
With the development of VLSI technology, a single chip can contain over one billion transistor. Multithreading technique is the developing trend of high performance processor in the future.
介绍了一种用软光刻技术制作微流芯片上PDMS微混合器的工艺。
A process of soft lithography was introduced for fabrication of PDMS (polydimethylsiloxane) micro-mixer on micro-fluidic chip.
随着深亚微米工艺的广泛应用，瞬态故障已成为芯片失效的主要原因。
Since deep submicron manufacturing process is widely used in microprocessors, transient faults have become the main source of chip faults.
利用数模混合信号CMOS工艺实现了一种新型漏电开关保护器芯片。
A new type of electrical leakage protection chip implemented in the digital analog mixed-signal CMOS process is represented.
此外，芯片的制作工艺也需要入射光线通过淀积在硅片上的电路，这使得光照度(光源照射在被照物体单位面积上的光通量)降低。
On top of that, the way chips are made requires the incoming light to pass through circuitry that has been deposited on to the silicon, reducing the level of illumination.
从芯片选择、改善热处理工艺以及如何选择硅胶等几个方面入手，本文讨论了如何有效地提高功率型LED封装工艺。
It is discusses the effect way to improve high power LED packaging technology, from dice selection, improve thermal management and how to select silicon Gel.
利用有限元法研究了堆叠芯片封装(SCSP)器件在封装工艺过程中的热应力分布。
The thermal stress distribution of SCSP in packaging process was studied by finite element method.
且该电路结构中肖特基二级管可在NMOSFET漏极直接制作肖特基金半接触来方便地实现，工艺简明可行又无须增加芯片面积。
Also, the added schottky diode can be easily realized by schottky contact in the drain of the NMOSFET, which does not add chip area.
圆片级芯片尺寸封装（WL-CSP）工艺是在固态芯片尺寸玻璃外壳中装入芯片。
This wafer level chip size package (WL-CSP) process encases the die in a solid die-size glass shell.
阐述了MEMS的主要封装工艺和技术，包括圆片级封装、单芯片封装、多芯片组件和3d堆叠式封装等。
Moreover, some major processes package of MEMS, including wafer-level packaging, single-chip packaging, multi-chip packaging and stacked 3d packaging, etc were discussed.
然而，芯片封装的最终质量受制作中每个工艺过程的影响。
However, the final quality of chips will be closely impacted by every factor during the process.
对压电蛋白传感芯片制备工艺进行质量控制，是提高芯片技术性能的关键。
Quality control of preparation technique is the key to develop technique performance of the piezoelectric protein sensing chip.
对压电蛋白传感芯片制备工艺进行质量控制，是提高芯片技术性能的关键。
Quality control of preparation technique is the key to develop technique performance of the piezoelectric protein sensing chip.
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