桶形移位器的设计采用了全译码电路结构。
Full-decoder circuit structure is used in Barrel Shifter design.
也证明了作为其一部分的多媒体移位器及多媒体部件的正确性。
Finally, the result proves that the multimedia unit and multimedia shifter are correct.
结果表明，该多媒体部件，包括多媒体移位器完全满足X微处理器的需要。
The result indicates that the multimedia unit including multimedia shifter can meet X microprocessor's need.
着重研究了整数加法器、移位器、先导零预测逻辑等浮点加法器关键部件的优化设计。
Integer adder, shifter and LZA these key parts are mainly studied and optimally designed.
重点讨论了其中的整数执行部件的设计，包括ALU、乘法器、桶式移位器、寄存器堆等重要执行部件。
It is given that the detailed design of the integer execution unit, include ALU, multiplier, barrel shifter and register files.
文章在进行循环移位运算的算法和性能分析的基础上，对循环移位器IP软核与硬核的设计作了详细阐述。
This paper discusses the design of hard and soft IP core of cycling shifter particularly on basement of analyzing the arithmetic and capability of cycling shift operation.
多个器件可以通过一个接口串联连接，该接口无需外部电平移位器或隔离器，就可沿着电池组来回发送数据。
Multiple devices can be connected in series through an interface that sends data up and down the battery stack without external level shifters or isolators.
将所设计的多媒体移位器放到X微处理器中进行系统级验证，并对整个X微处理器多媒体部件进行系统级验证。
The design achieves the goal of higher speed and smaller area. 3. The multimedia unit including multimedia shifter in X microprocessor is verified in system level.
变字长解码模块的核心是基于桶形移位器的并行解码结构，使用该结构的解码速度比一次一位的串行结构更快。
The serial structured decoder can decode one bit per cycle. Because the structure of UVLC(Universal Veriable Length Code) is fixed, "first one detector"is designed to decode UVLC.
采用数字移位器替代传统的除法器，使得电路结构大大简化，而且在很大的倍频系数范围内都保持很好的稳定性。
Use a binary digital shifter replace the traditional divider in ADPLL, make the structure simple and keeps the loop gain constant when the frequency multiplication factor changes.
文章对一种适用于分组密码算法的循环移位器ip核的设计进行了研究，该IP核的可重构设计使其具有可复用性。
A sort of reconfiguration cycling shifter for Block Cipher Algorithm, which was designed as IP core for reusing, was studied in this paper.
数字信号处理器包含了中央算术逻辑单元、乘法器单元、移位器单元、排序器单元、辅助寄存器单元、中断单元的设计。
The digit signal processor embodies the center arithmetic logic unit, Multiplier unit, Shifter unit, Sequencing unit, Auxiliary register unit, interception unit.
完成超越函数实现的数据路径设计，主要包括加法器、移位器、常数rom和旋转控制逻辑，同时针对“龙腾”C2微处理器的性能要求对各个部件进行优化设计。
Finish the design of data path, including adder, shifter, ROM and the control logic of the rotation, and optimize these parts in terms of the requirement of Longtium C2 microprocessor.
对于便携式电子产品来说，运算放大器可算是万能的信号调节电路，因为它可以执行滤波器、放大器、电压感测器、电平移位器、缓冲器、甚至开关等多种不同功能。
Operational amplifier is the most versatile signal conditioning block in any portable system. It can be a filter, an amplifier, an voltage detector, a level shifter, a buffer or even a switch.
要加载跨越16字节边界的值会十分困难，因为必须要将其存储到两个寄存器，进行移位然后再对它们进行掩码和组合。
To load a value which crosses a 16-byte boundary is even more difficult, as you would actually have to load it into two registers, shift them, and then mask and combine them.
这将总会是它为了将指定地址移到寄存器的开始所需向左移位的字节数。
This will always be the number of bytes it needs to shift left to move the address specified to the beginning of the register.
因此，只需将内容向左移位四个字节到新的寄存器来获得在首选槽内的低阶位。
Therefore, you just shift the contents to the left by four bytes into a new register to get the low-order bits in the preferred slot.
最后，寄存器4将拥有最终值，并且字节会移位进首选槽。
At the end of this, register 4 has the final value, with the byte shifted into the preferred slot.
我的设计目标就是最后的芯片数一定要尽量少，更准确的说，是要让最后的电路板尽量小，因此，这些小不点的串行移位寄存器中标了。
My design goal was to have the fewest chips in the end. More correctly it was to have the smallest board space used.
如果除法运算中的除数是2的幂，我们对这个除法运算还可以进一步优化，编译器会使用移位运算来进行这种除法运算。
We can make a division more optimized if the divisor in a division operation is a power of two. The compiler USES a shift to perform the division.
这就是移位寄存器，因为数据在每一个时钟脉冲的作用下通过寄存器会移动一位。
It is called a shift register because the data is shifted through the register by one bit position on each clock pulse.
移位寄存器应该置位或复位，才能产生所要求的序列。
The shift register should be set or cleared to produce the desired sequence.
本文研究的模型包括线性移位寄存器序列，前馈序列和钟控序列。
The models studied in this paper include linear shift register sequences, feedforward sequences and clock controlled sequences.
通过改变线性反馈移位寄存器的结构滤掉无效的测试矢量从而实现低功耗测试。
For low power consumption during test mode, the proposed approach ignores the non detecting vectors by altering the structure of LFSR.
利用传输门实现了32位桶式移位寄存器，其具体功能包括算术右移，逻辑左移，逻辑右移和循环右移。
In this paper, we realized Barrel Shifter of 32 bits by using transpost gates, its functions including arithmetic shift right, logic shift left, logic shift right and rotate right.
从16种编码开始，你可以用移位寄存器得到完全不同的数字模式。
From 16 starting codes, you got totally different digital patterns out of this shift register.
本文给出了有限域上多项式的友矩阵的某些性质，及其在计算线性移位寄存器序列的周期和循环码的最小长度的应用。
This paper gives some properties of companion matrix of polynomial over finite field with its application for evaluating period of linear shift register sequence and minimal length of cyclic code.
文中首先对线性移位寄存器序列和混沌序列做了阐述，并对其主要性能做了计算。
At first, this thesis expounds linear-shift-register sequence and chaotic sequence, and calculates the value of their main properties.
因为移位计数器的设计可查已有的反馈函数表达式，所以十分容易。
The design for shift counters is quite easy, because of the obtained feedback functions may be consulted.
主从机数据均在SPICLK的一个边沿移出移位寄存器，在另一个边沿锁存到移位寄存器。
The data is sent out from the shift register on one edge of the SPICLK and received on another.
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