用第四步中计算出的数字除以2(或是类似的转换因子)，由此把理想时间转换为持续时间。
Divide the figure you have calculated in step four by two (or similar conversion factor) in order to convert from ideal time to elapsed time.
直接数字频率合成(DDS)技术是目前广为应用的一项频率合成技术，它具有频率转换时间短、频率分辨率高、可编程等特点。
DDS (direct digital synthesis) is a sort of frequency synthesis technique, which has advantages such as short frequency conversion time, high resolution in frequencies, programmability and so on.
流水线ADC的模块有采样保持电路、乘法数模转换器、子ADC、数字校正电路、时钟产生电路和时间对齐电路。
The whole circuit consists of Sample and Hold Circuit, the Multiplicative A/D Converter, the Sub-ADC, the Digital Calibration Circuit, the Clock Generator and the Time Synchronizer.
此系统由程序接触器、自制的时刻比对自动转换器、时间间隔计数器和数字打印机组成。
The system consists of a programme contactor, a automatic transfer device which was completely designed and built by ourselves, a time interval counter and a digital recoder.
本论文在调研了以前时间数字转换电路工作的基础上，对用FPGA中的专用进位连线来实现时间数字转换电路的研究进行了全面详细的介绍。
Based on the survey of previous works, we put forward and introduce our method of realizing precise time-to-digital converter circuits by using the dedicated carry chain of FPGA.
FPGA中有着丰富的资源，目前已经有很多基于FPGA实现时间数字转换电路的研究工作。
There are many resources in FPGA. There are many works about using the resources of FPGA to realize time-to-digital converter circuits.
采用基于门延时的精细计数来量化被测时间间隔中与时钟不同步的部分，这样时间量就被转换成了数字量。
Both coarse count and fine count which base on the clock and gate delay separately were used to quantify them. Thus, time variable were converted into digital variable.
作为全数字锁相环的关键模块，时间数字转换器的性能在一定程度决定其性能的好坏。
As the core module of all-digital PLL, time-to-digital converter determines its performance largely.
可是，这种信号发生器的上限频率的提高受存储器的读取时间和数模转换器的转换速度的限制。为了提高数字法函数信号发生器的上限频率，我们提出了用分布存储式数字法生成函数信号。
However, extending the upper frequency of such function signal generator is limited by the read-out time of the memory and the conversion rate of the digital-to-analog converter.
可是，这种信号发生器的上限频率的提高受存储器的读取时间和数模转换器的转换速度的限制。为了提高数字法函数信号发生器的上限频率，我们提出了用分布存储式数字法生成函数信号。
However, extending the upper frequency of such function signal generator is limited by the read-out time of the memory and the conversion rate of the digital-to-analog converter.
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