本设计为兼顾模数转换器的速度和精度，采用数字校正技术，以每级1.5 位的9 级流水线结构实现。
The converter has a good tradeoff between conversion speed and conversion precision. It is a 1.5-bit per stage with 9 stage and digital correction technique.
该芯片采用了改进的直接数字频率合成算法、流水线结构与ROM分时复用技术，保证了芯片的高性能和速度，节省了芯片面积。
A modified direct digital frequency synthesis (DDS), pipelined structure, and time-sharing ROM are adopted in the chip, for saving chip area and ensuring high performance and speed.
数字信号处理(dsp)具有并行的硬件乘法器、流水线结构以及快速的片内存储器等资源，其技术广泛地应用于数字信号处理的各个领域。
DSP technologies have applied in every field of digital signal processing because of its parallel multiplier, pipeline structure and fast On-Chip memory.
数字信号处理(dsp)具有并行的硬件乘法器、流水线结构以及快速的片内存储器等资源，其技术广泛地应用于数字信号处理的各个领域。
DSP technologies have applied in every field of digital signal processing because of its parallel multiplier, pipeline structure and fast On-Chip memory.
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