支持外部等待时钟信号延长总线周期。
这样确定并使用时钟信号上升沿的位置作为定时测量。
This enables the position of the rising edges of the clock signal to be determined and used as a timing measurement.
本发明实施例提供了一种检测时钟信号的方法及装置。
The embodiment of the invention provides a method for detecting a clock signal and a device thereof.
可以提供输入及输出用于引入及输出精确参考时钟信号。
Inputs and outputs are provided for bringing in and outputting precision reference clock signals.
从设备发送给主机的数据时在时钟信号的下降沿读取的；
Data sent from the device to the host is read on the falling edge of the clock signal;
我们知道，在硬件电路设计中时钟信号是最重要的信号之一。
We know that the hardware circuit design clock signal is the most important one of the signals.
在串行数据输入（DI）或输出（DO）时使用的时钟信号。
Used as the synchronization clock when inputting (DI) or outputting (DO)serial data.
后者为屏上驱动电路提供控制、时钟信号，完成视频数据的处理。
The latter provides the control and clock signals for the driving circuitry on screen and accomplishes the video data processing.
本文主要详细讲述了如何利用差分变换后的波形提取位时钟信号。
The paper introduce the circuit on conversing difference signal to TTL , and introduce in detail how to gained bit-clock signal .
在时钟布线中，时钟信号和时钟偏差对电路性能的影响越来越明显。
In clock routing, clock signal and clock skew become more and more important for impact of the circuit performance.
你的微型计算机执行程序的速度将与你的时钟信号的速度成线性关系。
The speed with which your microcomputer executes programs will vary linearly with the speed of your clock signal.
输出时钟信号还具有可编程的相移和占空比调节等高级时钟变化功能。
The output clock signal has advanced clock shift ability such that the phase shift and duty cycle are programmable.
在这种情况下，内侧副韧带是内存时钟信号，而MDA是内存数据信号。
In this case, MCL is the memory clock signal, while MDA is the memory data signal.
本发明涉及在磁盘驱动器中产生用于写操作的同步时钟信号的方法和装置。
The invention relates to a method and device for generating synchronous clock signals for writing operation in disk drive.
从时钟利用主时钟发来的时钟信号，通过数字锁相环恢复出本地时钟信号。
With the signal from the master clock, the slave clock is able to recover an accurate local clock signal using a Clock Recovery Phase Locked Loop (PLL).
异步中断是由其他硬件设备产生的，可以在CPU时钟信号的任意时刻到来。
Asynchronous interrupts are generated by other hardware devices at arbitrary times with respect to the CPU clock signals.
这些持续不断的寄存器由电池供电，并接收来自晶体振荡器计时的时钟信号。
These persistent registers are powered by a battery and receive a timing clock signal from a crystal oscillator.
快速切换的信号，例如时钟信号，应该用地线屏蔽，以避免将噪声辐射到其他部分。
Fast switching signals, such as clock signals, should be shielded with digital ground to avoid radiating noise to other sections of the board, and clock signals.
它的功能是当感应到输入电压界限时提供一个锁存开关，通过外部时钟信号完成复位。
Its function is to provide a latching switch action upon sensing an input threshold voltage, with reset accomplished by an external clock signal.
同样通过降低电压和频率，C1E尝试比传统C1状态(只会停止时钟信号)提供更大的电能节省。
C1E tries to provide more power savings than the traditional C1 state (which only halts the clock signal) by also lowering the voltage and frequency.
该adc要求采用3.3V电源供电及差分采样时钟信号，以便充分发挥其工作性能。
The ADC requires a 3.3 V power supply and a differential sample clock for full performance operation.
电路采用了预启动和衬底电位选择结构，并利用三相时钟信号方式控制电荷泵的工作状态。
The latest three-phase clock signal control method was used to control the working state of charge pump.
时钟信号控制着数字系统的操作，它让逻辑门计算新的结果，然后由触发器存储执行结果。
Clock regulate the operation of a digital system by allowing time for new results to be calculated by logic gates and then capturing the results in flip-flops.
以sdram为基础采用DLL技术，并对时钟信号进行两次抓取资料，形成DDR技术。
Based on SDRAM, we adopt DLL technology and catch information twice on time signal, and it is so-called DDR technology.
系统VCO模块采用微分电路设计技术，可将电源噪音对时钟信号输出抖动的影响降至最低。
The VCO module makes use of differential coefficient circuit design technology to lower the effect of power resource on the clock signal input shake.
预处理器主要有延迟单元、乘法器和窄带滤波电路构成，可以从NRZ数据中得到时钟信号。
The preprocessor can extract clock information from NRZ data stream, which consists of a delay cell, a multiplier and a narrow-band filter.
相位频率检测器比较基准时钟信号和反馈时钟信号从而在一个或更多个输出信号中生成脉冲。
A phase frequency detector compares a reference clock signal to a feedback clock signal to generate pulses in one or more output signals.
时钟电路被配置为响应于具有输入供电电压和接地电压的时钟信号向内部节点提供上拉电流。
The clocking circuit configured to provide the pull-up current to an internal node in response to a clock signal having the input supply voltage and the ground voltage.
当基准和反馈时钟信号的相位和频率相同时，PLL处于锁定模式，且PFD输出信号中不生成脉冲。
When the phase and frequency of the reference and feedback clock signals are the same, the PLL is in lock mode, and the PFD does not generate pulses in its output signals.
当基准和反馈时钟信号的相位和频率相同时，PLL处于锁定模式，且PFD输出信号中不生成脉冲。
When the phase and frequency of the reference and feedback clock signals are the same, the PLL is in lock mode, and the PFD does not generate pulses in its output signals.
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