可以预计，只要在器件上作某些更换，亦可制成工作速率更高的时钟数据恢复模块。
It is estimated that a data and clock recovery module with a higher operating rate is available only if some devices are changed.
与传统并行数据恢复电路相比，该电路不需要本地参考时钟，并且恢复出的并行数据是位同步的。
Compared with conventional circuits, the recovered parallel data is bit-synchronous, and the reference clock is avoided.
设计了一个数字时钟数据恢复电路，采用相位选择锁相环进行相位调整，在不影响系统噪声性能的前提下大大降低了芯片面积。
A phase selection PLL is adopted to adjust the phase of the recovered clock, and the chip area of the recovery circuit is greatly reduced without sacrificing the noise performance of the system.
在突发式的接收模块中，逻辑电平的恢复和时钟数据的恢复是其关键的问题。
The most difficult problem in burst mode receiver would be signal logic level recovery and data and clock recovery.
基于SERDES的串行通信过程中采用时钟和数据恢复技术（CDR）代替同时传输数据和时钟，从而解决了限制数据传输速率的信号时钟偏移问题。
Serial communications based on SERDES adopt the clock_data recovery(CDR) instead of both data and clock transmitting, which solve the problem of clock skew.
本系统利用集成时钟和数据恢复芯片SY87700L实现了可靠的位同步。
This system select integrate chip SY87700L to realize bit synchronizing reliably .
在发送端时钟频率随时间变化的情况下，以较低的成本和较简单的电路实现，保证了接收端采样数据及音频数据恢复的准确性。
Because clocking frequency of sending terminal is changed with times at lower cost and simple circuit, accuracy of receiving end sampled data and audio - data recovery is assured.
在发送端时钟频率随时间变化的情况下，以较低的成本和较简单的电路实现，保证了接收端采样数据及音频数据恢复的准确性。
Because clocking frequency of sending terminal is changed with times at lower cost and simple circuit, accuracy of receiving end sampled data and audio - data recovery is assured.
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