简述了基于FPGA/CPLD技术的数字频率计的总体设计。
This paper illustrates the general design of digital frequency meter based on FPGA/CPLD Technology.
介绍了一种利用EDA技术设计的数字频率计。
This paper discusses the digital cymometer design principles by using EDA technology.
本文介绍了一种同步测周期计数器的设计，并基于该计数器设计了一个高精度的数字频率计。
The design of a counter measuring synchronous period is introduced in this paper. And based on it, a high precision digital cymometer is designed.
在对转速和金属裂纹的数字检测中，我们应用pmos和CMOS组件设计了两种数字频率计。
In measuring the speed of rotation and the depth of metal crack, PMOSICs and CMOSICs were employed to design two kinds of digital frequency counters.
实验四频率计实验要求：设计一个有效位为4位的十进制的数字频率计。
Experiment iv Cymometer experimental requirements: design of an effective place for the 4 decimal digital frequency meter.
该设计比以前老式的设计有较大改进，使数字频率计具有高精度和高速的特点。
There was greater improvement to it's time to design the design more outdated than before, made the digital cymometer have high accuracy and high-speed characteristic.
该设计比以前老式的设计有较大改进，使数字频率计具有高精度和高速的特点。
There was greater improvement to it's time to design the design more outdated than before, made the digital cymometer have high accuracy and high-speed characteristic.
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