本文介绍一种实用的全数字锁相环方案。
This paper introduces a practic design version of all-digital PLL.
提出了一种具有自动变模控制的快速全数字锁相环。
A fast all digital phase-locked loop with automatic modulus control is presented.
设计了一种用于通信系统载波同步的新数字锁相环。
A novel all-digital phase locked loop (PLL), applied to the carrier synchronization of communication systems, is designed.
数字锁相环路（DPLL）是数字相干解调技术的核心。
The Digital Phase Lock Loop(DPLL)is the core of the coherent demodulation.
本文讨论的全数字锁相环包括过零检测器和环路滤波器。
This paper discusses an all digital phase-locked loop with a zero-crossing detector and a loop filter.
提出了一种低功耗、快速锁定全数字锁相环的设计方法。
A design method for all DPLLs that with low power cost and high phase locked velocity has been proposed.
采用数字锁相技术从噪声中提取有效信号，以减小测量误差。
The digital lock-in technique is used to rather extract the effective signal from the noise and reduce the measurement error.
提出了一种用于光纤陀螺信号检测的数字锁相放大器的设计方法。
In this paper, a kind of digital lockin amplifier used in FOG signal detection is designed.
从时钟利用主时钟发来的时钟信号，通过数字锁相环恢复出本地时钟信号。
With the signal from the master clock, the slave clock is able to recover an accurate local clock signal using a Clock Recovery Phase Locked Loop (PLL).
数字锁相环在实际通信系统中应用广泛，但其精确的环路参数设计比较困难。
Digital phase lock loops are widely adapted in nowadays communication systems. However, it is difficult to design the loop parameter precisely.
本文主要研究了基于全数字锁相环的谐振型逆变器频率跟踪的数字化控制方案。
The paper studies digital control scheme of resonance inverter frequency-tracking based on all digital phase-locked loop.
本文介绍了一种利用混合数字锁相环(HDPLL)实现码元定时恢复的新方法。
Anovel approach to implement symbol timing recovery is presented which USES a hybrid digital phase locked loop (HDPLL).
重点研究了基于FPGA的全数字锁相环频率跟踪技术和数字化SPWM实现技术。
All digital Phase-Locked Loop frequency tracking and digital SPWM realization technology based on FPGA are emphasized in the research.
作为全数字锁相环的关键模块，时间数字转换器的性能在一定程度决定其性能的好坏。
As the core module of all-digital PLL, time-to-digital converter determines its performance largely.
设计了基于模拟滤波器和基于数字锁相放大技术的两种红外气体传感器的信号处理方法。
Two signal processing methods, one based on analog filters, the other based on digital lock-in amplifying technique, are developed and analyzed.
对于其中的单稳态电路的数字化和数字锁相环提取位同步信号也进行了详细的设计说明。
The digital realization of monostable circuit and extraction of bit-synchronous signal with digital phase lock loop are also introduced in detail.
本文分析了数字锁相环路的寄生频偏，它是现代通讯系统中频率合成器的重要指标之一。
This paper gives an analysis of parasitic frequency deviation in the digital phase locked loop, which is one of the important specifications of modern communication systems.
采用高精度的直接数字频率合成（DDS）和数字锁相环技术，实现了高频率跟踪精度。
DDS and digital phrase-lock technology have been applied in FPGA to improve the accuracy of frequency tracking.
它用高精度数字锁相环，精确地恢复地球同步气象卫星采集的原始云图数据的同步基准信息。
It USES a high precision digital phase-locked loop (PLL) to accurately recover the Synchronous reference information of raw cloud-cover image data collected by the geostationary satellite.
前者在常规的采用电压外环、电流内环的双闭环控制基础上，搭建数字锁相环、数字滤波器。
Digital PLL and digital filter are built based on conventional double closed-loop control which contains voltage loop and current loop.
本文提出一种用于光盘径向伺服系统的带有快速数字锁相环的精密位置跟踪环路的设计方案。
The design of precise position tracking loop for DRTS with fast digital phase-locked loop is described.
按照可列一阶马尔可夫链方式，建立了一个具体的二阶数字锁相环的模型，并对它进行了分析。
A specific second-order digital phase-locked loop is modeled after a first-order Markov chain with alternatives, aud analyzed.
研究了数字锁相实施玫瑰线扫描同步采集方位转换和红外多帧配准图像模糊分割识别系统实现。
The real-time and parallel processing ability of the system is investigated. The phase-lock azimuth transform and infrared registration recognition are implemented in the system.
本文根据突发式数字通信快速锁相要求，提出一种位同步信号提取的新的快速全数字锁相环方案。
This paper presents a new type of all digital phase-locked loop(ADPLL)used for extracting a bit-synchronous signal to meet the requirements of the fast phase-locked in burst digital communication.
针对光伏并网发电系统，基于数字锁相环，研究了一种实现系统并网电流幅值、相位跟踪控制的新方法。
Based on a new digital PLL, a new current tracing control strategy for a grid-connected PV system was proposed to control the amplitude and phase of the inverter current.
第四章探讨了运用可编程技术设计数字锁相环和数字倍频器的相关问题，为以后电路设计拓展更多的方法。
The chapter 4 discuss some question of the circuit using programmable device like digital phase locked loop and digital frequency multiplier, it can increase the way of circuit design.
位同步时钟信号的提取是通信系统中的关键部分，应用数字锁相环可以准确地从输入码流中提取出位同步信号。
Bit synchronous clock recover circuit is the key part of the communication system, it can exactly recover the synchronous signal from input data stream.
应用过采样和数字锁相检测技术能提高动态光谱法中光电脉搏波信号的检测精度， 文章对此进行了理论推导。
The precision of measure can be advanced by making use of over-sampling and lock-in amplifying on the pick-up of photoelectric pulse wave in DS detection.
应用过采样和数字锁相检测技术能提高动态光谱法中光电脉搏波信号的检测精度， 文章对此进行了理论推导。
The precision of measure can be advanced by making use of over-sampling and lock-in amplifying on the pick-up of photoelectric pulse wave in DS detection.
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