脉冲选择器电路向通过垂直移位寄存器电路而选择出的任意的像素行供给驱动脉冲。
A pulse selector circuit supplies a drive pulse to the desired pixel row selected by the vertical shift register circuit.
本文讨论分析了用作向量寄存器电路的超高速移位寄存型结构特点和性能，利用计算机辅助进行了计算分析验证，并论证了有关检查方法。
In this paper the structure features and performance of a high-speed shift register which is used as vector register are discussed and analysed. The analysis is verified by computer-aided calculation.
我的设计目标就是最后的芯片数一定要尽量少，更准确的说，是要让最后的电路板尽量小，因此，这些小不点的串行移位寄存器中标了。
My design goal was to have the fewest chips in the end. More correctly it was to have the smallest board space used.
当主控门打开时，经过转换的输入信号脉冲通过它进入计数寄存器，并在此统计，然后通过显示电路输出。
While the main gate is open, the conditioned input signal pulses are passed through to the counting register, where they are tallied and then scaled for output by the display circuitry.
每个器件都有一个八位CMOS移位寄存器和CMOS控制电路，八个CMOS数据锁存，八个双极电流吸收达林顿输出驱动器。
Each device has an eight-bit CMOS shift register and CMOS control circuitry, eight CMOS data latches, and eight bipolar current-sinking Darlington output drivers.
验证是当前越来越复杂的集成电路设计中的瓶颈，在寄存器传输级（RTL）直接做验证是目前比较有效的一种途径。
Verification is the bottleneck of more and more complex integrated circuit designs, and doing verification directly on register transfer level (RTL) is a promising solution.
为了提高时序电路的等价性验证速度，提出一种改进的基于寄存器匹配的验证算法。
An improved algorithm based on register mapping is proposed to increase the speed of equivalence checking for sequential circuits.
移位寄存器是用来寄存二进制数字信息，并能将存储的信息移位的时序逻辑电路。
The shift register is a sequential logical circuit, which can store and shift binary digit information.
寄存器传输级（RTL）描述是目前应用最广泛的电路设计描述形式。
The Register Transfer Level (RTL) behavioral descriptions are widely used in IC designs.
本文主要是对大规模、超大规模集成电路寄存器传输级（RTL）的自动测试产生算法进行研究。
This dissertation focuses on automatic test generation (ATPG) algorithms for very large-scale integrated circuits at register-transfer-level (RTL).
集成电路设计在寄存器传输级的设计方法已经非常成熟。
介绍了一种对定时器、计数器、数据寄存器的数据进行外部设定并显示的电路，并给出了相应的梯形图程序。
This paper introduces a circuit setting up and displaying the data of timer, counter and data register out of PLC. It gives the ladder-type Patterned program.
提出了中断执行周州复川、寄存器模型设计中断标识信号的中断电路实现方法。
A design method based on multiplexing execution-cycle and interrupt flag signals using register model is proposed. S.
接着，针对生成矩阵的准循环特性，提出了一种新的基于反馈移位寄存器的编码电路，并用FPGA进行了实现。
Next, according to the characteristics of quasi-cyclic matrix, a new encoding circuit using feedback shift registers is proposed and implemented by FPGA.
对RS编码器采用移位寄存器形式，来实现除法电路求得监督位。
Check bit of divide operation circuits of rs codes is realized by using shift registers.
一种改进的基于闪速EEPROM存储器的存储子系统，包括一个或多个闪存阵列，每一个都带有两个数据寄存器和一个控制器电路。
An improved flash EEPROM memory-based storage subsystem includes one or more flash memory arrays, each with a duplicity of data registers and a controller circuit.
第五章设计了全p沟道tft构成的屏上驱动电路，包括反相器、移位寄存器、传输门的设计，并用仿真软件进行了仿真验证。
In chapter 5, the on-screen driving circuits composed of P-channel TFT have been designed, including inverter, shift register, transmission gate and simulated using simulation software.
所述控制电路选择存储有信息的所述寄存器，以便在最优写条件下进行编程。
The control circuit selects the register storing information for performing programming under the optimal write condition.
双向移位寄存器是一种中规模集成电路，可构成移位寄存器型计数器。
Bidirectional shift register is a kind of medium-scale integrated circuits, it can be used to compose various counters conveniently.
一种集成电路，包括多个逻辑元件(LE)和一个部分扫描寄存器，每个逻辑元件具有多个输出。
An integrated circuit is described as comprising a plurality of logic elements (LEs), each of which having a plurality of outputs, and a partial scan register.
在通信协议中，主要实现了双向数据缓冲器、数据移位寄存器、时钟控制电路以及奇偶校验等功能。
The protocol realized some functions, such as two-way data buffer, shift register, clock circuit and parity check.
文章详细讨论了RTCC、OPTION寄存器、预定标器及同步延时单元的电路结构、工作原理及设计特点。
The paper details the RTCC, OPTION register, prescaler and sync delay circuit principle and design feature.
系统设计了A16/D16寄存器基接口电路，开发了软面板和仪器驱动程序。
The method to achieve circuit of A16/D16 register-based interface is put forward, the softpanel and drivers to apparatus are developed.
在电流工作方式下，通过设计优化的存储单元、新型高速电流灵敏放大器以及一种灵敏放大器控制信号产生电路，提高了寄存器堆的读取速度。
High speed is achieved by using current mode techniques, which include designing optimum register cell, new high speed current sense amplifier and sense amplifier control signal generator.
分析了CMOS逻辑门电路在运行时的电流特征，阐明了集成电路中数据与电磁辐射的相关性，建立了寄存器级电磁信息泄漏汉明距离模型。
The result shows that EM information leakage exists in CMOS integrated circuit during work, XOR operation in each round of DES is an attack point.
第四章在FPGA平台上实现载波同步单元电路，并给出了实现后的FPGA资源消耗、寄存器传输逻辑(rtl)原理图。
In chapter 4, the circuit of the carrier synchronization unit is implemented on FPGA, the Resistor Transistor Logic (RTL) schemes are presented.
硬件电路包括AT 89 C52单片机、显示电路、键盘电路、74ls164寄存器等。
Hardware circuit including AT89C52, display circuit, keyboard circuit, 74ls164 registers, etc.
采用反馈移位寄存器与逻辑门设计了三个典型的编码器电路：基于SRAA电路的串行准循环LDPC码编码器；
Three encoder circuit are designed respectively with feed shift-registers and logic gates: SRAA-based serial QC-LDPC encoder;
采用反馈移位寄存器与逻辑门设计了三个典型的编码器电路：基于SRAA电路的串行准循环LDPC码编码器；
Three encoder circuit are designed respectively with feed shift-registers and logic gates: SRAA-based serial QC-LDPC encoder;
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