本文主要介绍了CC2420的管脚结构及功能、寄存器寻址、与微处理器P89LPC924的通信以及CC2420的状态控制流程。
This paper introduces the pins configuration and function of CC2420, the register access, communication with the MPU P89LPC924 and the state controlling flow.
在这两种汇编器中，寄存器的名称是一样的，但是因为寻址模式不同，使用它们的语法是不同的。
In both the assemblers, the names of registers remain the same, but the syntax for using them is different as is the syntax for addressing modes.
正被寻址的Modbus寄存器的类型（input、hold、coil、status）。
The type of Modbus register being addressed (input, hold, coil, status).
[requestcommand]的长度也是一个字节，它的值基于正被寻址的寄存器的类型设置。
[Request command] is also 1 byte long, and its value is set based on the type of registers being addressed. For reading register values.
所有实际的处理都发生在寄存器之间(或寄存器和立即寻址模式操作数之间)。
All of the actual processing takes place between registers (or between registers and immediate-mode operands).
最后，在索引寄存器间接寻址模式中，基址和索引都保存在寄存器中。
Finally, in indexed register indirect addressing mode, both the base and the index are stored in registers.
因此，使用基指针寻址模式，我们可以指定寄存器x作为基指针，8作为偏移量。
So, using base-pointer addressing, you would specify register X as the base pointer and 8 as the offset.
在基指针寻址模式中，寄存器中保存的是基址，数字是偏移量。
In base-pointer addressing mode, the register has the base address and the literal number has the offset.
寄存器间接寻址模式使用一个寄存器来指定内存访问的整个地址。
The register indirect addressing mode uses a register to specify the whole address for the memory access. This is used for numerous situations, including, but not limited to
在总线上的每个控制器可以被CPU所单独寻址，这是软件设备驱动程序能写入寄存器并能控制这些控制器的原因。
Each controller on a bus can be individually addressed by the CPU, this is why the software device driver can write to its registers and thus control it.
一种图形处理单元流水线，通过传送来自第一模块的围篱指令至寻址同步寄存器对而执行同步。
A GPU pipeline is synchronized by sending a fence command from a first module to an addressed synchronization register pair.
围篱指令相关数据可被储存在寻址寄存器对的围篱寄存器。
Fence command associated data may be stored in a fence register of the addressed register pair.
围篱指令相关数据可被储存在寻址寄存器对的围篱寄存器。
Fence command associated data may be stored in a fence register of the addressed register pair.
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