所述字线驱动器驱动用于所述行存储器单元的字线。
The word line drivers drive word lines for the rows of memory cells.
本发明公开了存储器单元阵列，以多行与多列排列。
The invention discloses a memory cell array arranged multiple in rows and lines.
本发明提供了电源电平升高的可编程逻辑器件存储器单元。
Programmable logic device memory elements with elevated power supply levels are provided.
而且，更新部在电源下降时对存储器单元进行读出及重新写入。
The refresh portion reads and rewrites data from and in the memory cell in a power-down state.
本发明提供一种用于读取存储器单元的状态的读出放大器电路。
A sense amplifier circuit for reading the state of memory cells.
所述存储器阵列包括M行和N列存储器单元以及列虚设单元。
The memory array includes M rows and N columns of memory cells and a column of dummy cells.
位于绝缘层上的位线电连接到多个电阻存储器单元中的最后一个。
A bit line on the insulating layer is electrically connected to a last one of the plurality of resistive memory cells.
所述读出放大器基于所述启用信号检测用于所述列存储器单元的位线。
The sense amplifiers detect bit lines for the columns of memory cells based on the enable signals.
本发明公开了一种位于基底上的电阻式存储器单元和电阻式存储器阵列。
The invention is directed to a resistive memory cell on a substrate and a resistive memory array.
数据加载和读取电路向存储器单元中加载数据并从存储器单元读取数据。
Data loading and reading circuitry loads data into the memory elements and reads data from the memory elements.
本发明提供一种具有多层隧道绝缘体的存储器单元晶体管及存储器器件。
The invention provides a memory cell transistor having multi-layer tunnel insulator and memory device.
所述集成电路包括具有二极管及与所述二极管连通的反熔丝的存储器单元。
Such integrated circuit includes a memory cell with a diode and an antifuse in communication with the diode.
本发明的优点在于减少存储器单元的大小、减低编程扰动、以及按页擦除的能力。
The advantage thereof is to reduce size of the memory cell, reduce programming interference, with paged erasing function.
该存储器备有：非易失性的存储器单元和对存储器单元进行重新写入用的更新部。
This memory comprises a nonvolatile memory cell and a refresh portion for rewriting data in the memory cell.
本发明公开了一种多阻态电阻随机存储器单元及其制备方法，属于微电子技术领域。
The invention discloses a multi-resistance state resistor random-access memory unit and a preparation method thereof, and belongs to the technical field of microelectronics.
由此，可以得到能够抑制由积累的干扰而导 致的存储器单元的数据消失的存储器。
A memory capable of preventing a memory cell from disappearance of data resulting from accumulated disturbances is obtained.
此外，利用反向偏置所述存储器单元的二极管的编程脉冲对所述存储器单元进行编程。
Further, the memory cell is programmed utilizing a programming pulse that reverse biases the diode thereof.
在正常操作过程中，可以按比可编程核心逻辑电源电压高的电源电压对存储器单元供电。
During normal operation the memory elements may be powered with a power supply voltage that is larger than the programmable core logic power supply voltage.
在这个例子中，静态随机存储器单元的金属层已被修改，以降低金属节点之间短路的概率。
In this example, the metal one layer of a SRAM cell has been modified to reduce the probability of shorts between metal one nodes.
在一种可能的设计中，晶体管100、102、104和106每一者是存储器单元或元件。
In one possible design, transistors 100, 102, 104 and 106 are each memory cells or elements.
另一实施例包括施加较低的编程电压，以将所述最末字线的存储器单元编程为选择物理状态。
Another embodiment includes applying a lower program voltage to program memory cells of the last word line to select physical states.
在数据加载操作过程中，可以按与可编程核心逻辑电源电压相等的电源电压对存储器单元供电。
During data loading operations, the memory elements may be powered with a power supply voltage equal to the programmable core logic power supply voltage.
一种二端口SRAM存储器单元(20)包括耦合到存储节点的一对交叉耦合的反相器(40)。
A two-port SRAM memory cell (20) includes a pair of cross-coupled inverters (40) coupled to storage nodes.
一种电荷陷获非易失存储器单元的阵列，排列为多列单元，且每一列为串联安排，如NAND串。
An array of charge trapping nonvolatile memory cells is arranged in several columns of cells, each arranged in a series, such as a NAND string.
向存储器单元中加载可编程逻辑器件配置数据，来对可编程核心 逻辑进行配置以执行定制逻辑功能。
Programmable logic device configuration data is loaded into the memory elements to configure the programmable core logic to perform a custom logic function.
当存储器单元结构的其它部分储存不相关的信息时，读取作业将不同部分的电荷捕捉结构之间的耦合减少。
When the other parts of the memory cell stores irrelated information, read operation reduces the coupling between charge capturing structures of different parts.
所述电阻式存储器单元包括第一栅极、第二栅极、共用掺杂区域、接触窗插塞、位线以及电阻式存储器元件。
The resistive memory cell comprises a first gate, a second gate, a common doped region, a contact plug, a bit line and a resistive memory element.
通过增加存储器单元上的净正电荷以擦除存储器单元，而通过增加存储器单元上的净负电荷以编程存储器单元。
By increasing net positive charges on the memory cell, it erases the memory cell and by increasing net negative charges on the memory cell, programs the memory cell.
在编程此反熔丝一次可编程非易失存储器单元后，已编程的区域(例如为连结)可作为二极管，其形成于反熔丝上。
A programmed region, i. e., a link, functioning as a diode, is formed on the anti-fuse after the anti-fuse OTP nonvolatile memory cell is programmed.
在编程此反熔丝一次可编程非易失存储器单元后，已编程的区域(例如为连结)可作为二极管，其形成于反熔丝上。
A programmed region, i. e., a link, functioning as a diode, is formed on the anti-fuse after the anti-fuse OTP nonvolatile memory cell is programmed.
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