本文主要研究的是基于现场可编程逻辑阵列（FPGA）的数字上下变频技术的设计和实现。
This paper deals with the design and implementation of Digital Up Conversion and Digital Down Conversion based on the field-programmable gate array (FPGA).
在硬件、软件上进行了优化设计特别是采用了大规模可编程逻辑器件ISPLSI- 1032E门阵列使该系统更简洁、稳定。
Especially, the system becomes more concise and stable by use of large scale programmable logic device ISPLSI - 1032e gate array.
大规模可编程逻辑阵列（CPLD）的快速开发、在系统编程以及高速可靠的特点使得CPLD在数字系统的构建中起到越来越重要的作用。
The feature of rapidly develop, high speed and high reliability of Complex Program Logic Device(CPLD) makes CPLD playing a more and more role in the design of digital system.
在此基础上，采用高速数字信号处理器、大规模可编程逻辑门阵列和实时软件进行系统设计，完成了原理样机的研制。
On this basis, the principle prototype is developed with high speed digital signal processor (DSP), the huge reprogrammable logic gate arrays (FPGA) and real-time software.
在恶劣电磁环境下，对现场可编程逻辑阵列（FPGA）工作稳定性影响较大的是外界杂波脉冲和毛刺信号。
This paper introduces that some measures of restraining pulse jamming and enhancing the stability of FPGA chips in bad electromagnetic circumstance.
该驱动板以现场可编程逻辑门阵列为DSP与编码器、脉冲命令和功率模块等电路之间的接口，以最新的智能功率模块(IPM)作为功率输出驱动芯片。
FPGA is used as interface between the DSP and the encoder, pulse command and power module. The latest intelligent power module (IPM) is used to provide the function of power stage.
可编程逻辑，特别是现场可编程门阵列(FPGA)便是这样的解决方案。
Programmable logic, in particular field programmable gate array (FPGA) is such a solution.
本文介绍了一种特殊的硬件实现方法，使用了管脚少、成本低、容易得到的逻辑接口器件，例如可编程逻辑阵列（PAL）、可编程逻辑电路（CPLD）或者FPGA。
The article introduces a unique hardware realization, which utilizes less-foot, low-cost and easy-to-get logistic interfaces, as PAL, CPLD or FPGA.
本文介绍了一种特殊的硬件实现方法，使用了管脚少、成本低、容易得到的逻辑接口器件，例如可编程逻辑阵列（PAL）、可编程逻辑电路（CPLD）或者FPGA。
The article introduces a unique hardware realization, which utilizes less-foot, low-cost and easy-to-get logistic interfaces, as PAL, CPLD or FPGA.
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