通过控制一个N位累加器累加，取其最高位，即可得到可编程时钟源。
Through controlling an N-bit accumulator and then get its highest bit to generate the programmable clock.
该文介绍了如何利用可编程控制器的日历时钟功能，对一灯饰控制系统进行自动控制，从软件、硬件两个方面介绍了具体实现的方法。
The paper presents a lighting decoration control system, in which clocking function of PLC is used and automatic timing control of lighting decoration system may be realized.
介绍了可编程控制器机内时钟的设定及时间控制的方法，给出了编程实例。
This paper passes on clock setting and time controlling methods on PLC, and gives program examples.
在各个实施例中，该方法可包括配置不同的可编程测试时钟控制器来基本上并行地测试不同域。
In various embodiments, the method can include configuring different programmable test clock controllers to test different domains substantially in parallel.
用复杂可编程芯片(CPLD)实现，并用于雷达数字光纤通信系统的信道编码，提高了时钟提取的性能。
The scheme can be implemented by using the CPLD chip, and used for the channel coder in a radar digital optic-fiber communication system and improving the features of clock extraction.
输出时钟信号还具有可编程的相移和占空比调节等高级时钟变化功能。
The output clock signal has advanced clock shift ability such that the phase shift and duty cycle are programmable.
一个极宽的可编程频率范围允许时钟以一个1ms至9.5小时的周期运作。
An extremely wide programmable frequency range allows the clock to operate with a period from 1ms to 9.5 hours.
本实用新型公开一种时钟同步倍频电路，尤其涉及电路设计和可编程逻 辑器件设计中时钟倍频电路。
The utility model discloses a clock synchronized frequency multiplication circuit, in particular relating to clock synchronized frequency multiplication circuit in circuit design and PLC design.
本实用新型公开一种时钟同步倍频电路，尤其涉及电路设计和可编程逻 辑器件设计中时钟倍频电路。
The utility model discloses a clock synchronized frequency multiplication circuit, in particular relating to clock synchronized frequency multiplication circuit in circuit design and PLC design.
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