系统设计主要包括加法电路，A/D模数转换模块，串口通信模块，上位机显示模块等部分。
System design mainly includes the addition circuit, A/D analog-to-digital conversion module, serial communication module, PC display module, etc.
数字加法器需要更多的电路、因而需要更大的功率才能工作，但它不需要这么高的准确性。
A digital adder needs more circuitry, and thus more power, to operate, but it does not require such high accuracy.
基于该理论，本文设计了实现三值加法和三值乘法的电流型CMOS电路。
Based on this theory, the current-mode CMOS circuits realizing ternary addition and ternary multiplication operations are designed.
主要研究方向是优化浮点加法器结构，减小浮点加法运算的延迟，优化电路结构。
The main research area is the structure optimization of floating-point adder, which is intent to minimize the delay of floating-point addition and optimize the circuit structure.
主要研究方向是优化浮点加法器结构，减小浮点加法运算的延迟，优化电路结构。
The main research area is the structure optimization of floating-point adder , which is intent to minimize the delay of floating-point addition and optimize the circuit structure.
要转换一个布尔表示式成选通电路，评估表示使用操作标准顺序：传统的增殖加法和操作在括号之内且在别的之前。
To convert a Boolean expression to a gate circuit, evaluate the expression using standard order of operations: multiplication before addition, and operations within parentheses before anything else.
LOP电路设计采用VHDL语言门级描述，已通过逻辑仿真验证，并在浮点加法器的设计中得到应用。
The LOP circuit module is described in gate level with VHDL, which has passed the logic simulation and verification. It is applied to the design of floating-point adder.
给出了一种异步实现结构的异步加法单元、异步比较单元和异步选择单元电路。
The circuits of asynchronous adder unit, asynchronous comparator unit, and asynchronous selector unit are proposed.
电子计算机是由具有各种逻辑功能的逻辑部件组成的，加法器就属于其中的组合逻辑电路。
A computer is comprised of some logic parts which have serial logic functions, and the adder is one of the combine logic circuits.
分析了一个异步十进制加法计数器实验电路的错误，介绍了异步十进制加法计数器典型电路。
This paper analysis the errors of experimental circuit on a asynchronous decimal carry counter, introduces a typical circuit on a asynchronous decimal carry counter.
笔者现已成功地设计了1024位循环式加法器，并应用到RSA密码体系的硬件电路中，得到了较好的效果。
The authors have succeeded in devising a1024bit circular adder and it has been used in the circuit of RSA cryptosystem with a good effect.
该方案的系统组成包括PC机软件、LXI接口电路、控制模块、多通道dds系统和加法器。
This system could include the PC software, LXI interface circuit, control module, multi-channel DDS system, and the Adder module.
在本文中，我们提出8种不同的全加器电路，分别皆使用4位元链波进位加法器将其实现。
We proposed 8 kinds of full adder and all of them are realized in 4 bit ripple carry adder.
设计了4位QSERL串行进位加法器(RCA)电路，和相应的CMOS电路进行了功耗比较。
QSERL 4 bit carry ripple adder (RCA) is designed and compared with static CMOS counterpart.
检测电路通过硬件实现乘法和加法运算，得到实时补偿的无功功率大小。
The measuring circuit can achieve real-time reactive power to be compensated by using hardware operations, such as multiplication and summation.
文中首先介绍了内建自测试的实现原理，在此基础上以八位行波进位加法器为例，详细介绍了组合电路内建自测试的设计过程。
The BIST of the principle of achieving is introduced first in this paper, then take the 8-bit ripple carry adder as an example, describes the design process of BIST.
文中首先介绍了内建自测试的实现原理，在此基础上以八位行波进位加法器为例，详细介绍了组合电路内建自测试的设计过程。
The BIST of the principle of achieving is introduced first in this paper, then take the 8-bit ripple carry adder as an example, describes the design process of BIST.
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