Wire length estimation techniques are studied which is correlated to FPGA routing channel design.

研究了与FPGA通道设计密切相关的互连线长估计技术。

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Experimental results show that our placement scheme achieves on average a total decrease of 27% in delay, 34% in wire-length and 42% in runtime, compared with the traditional placement methods.

实验结果表明，我们的布局算法与传统的布局算法相比，在时延上平均减少27%，在线长上平均减少34%，在运行时间上平均减少42%。

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Experimental results show that our placement scheme achieves on average a total decrease of 27% in delay, 34% in wire-length and 42% in runtime, compared with the traditional placement methods.

实验结果表明，我们的布局算法与传统的布局算法相比，在时延上平均减少27%，在线长上平均减少34%，在运行时间上平均减少42%。

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