Testing is the expensive and difficult section of VLSI design.
测试是VLSI设计中费用最高、难度最大的一个环节。
In VLSI design flow, design rule checking (DRC) is an important step.
集成电路(VLSI)设计流程中，设计规则检查(DRC)是关键一环。
A grid less routing algorithm for VLSI design is presented in this paper.
本文提出一种高性能超大规模集成电路无网格布线算法。
In VLSI design, the hardware reuse technique is employed to save area costs.
在VLSI设计上实现了模乘和求逆运算的硬件复用，大幅度地降低了成本。
It is a very high speed VLSI Design through the pipeline architecture with power optimization.
该设计采用流水线处理结构，能达到非常快的处理速度，同时进行了功耗优化。
The traditional magnitude comparator is based on gate-level techniques and not suitable for VLSI design.
传统的数字比较器采用门级设计技术，电路结构不规则，不利于大规模集成电路的设计。
The VHDL design organization and data types are described. Applications of VHDL to VLSI design are discussed.
概要地介绍了VHDL的设计组织和数据类型，并对VHDL的特点及其在VLSI设计中的应用要点做了一些探讨。
This is an electronic book is on CMOS VLSI design principles and systems prospects, and I hope to have your help!
这是一本电子书，是关于CMOSVLSI设计原理和系统展望的，希望对您有所帮助！
From the introduction of design process of every module circuit, we can see easily some general feature of VLSI design with HDL.
通过对各个模块设计过程的介绍，阐明了使用HDL语言设计超大规模集成电路的一般特点。
The access time is important for the system chip with high performance, the low power has been the spotlight and challenge in VLSI design.
高性能的系统芯片对数据存取速度有了更严格的要求，同时低功耗设计已成为VLSI的研究热点和挑战。
From the introduction of design process of every module circuit, we can see easily some general feature of VLSI design with HDL. methodology.
通过对各个模块设计过程的介绍，阐明了使用HDL语言设计超大规模集成电路的一般特点。
Decision diagram model is a utility to represent data dependence between signals in VLSI designs, and is widely used in VLSI design verification.
决策图模型描述了VLSI设计信号间的数据依赖关系，在VLSI设计验证中有广泛的应用。
This article has studied the function verification method which in the traditional VLSI design USES, has analyzed each method characteristic and the deficiency.
本文在研究了传统的VLSI设计中采用的功能验证方法后，分析了各种方法的特点和不足之处。
The design of asynchronous circuits is widely used in modern VLSI design, which is able to resolve the problems of power dissipation, system speed, clock skew, etc.
异步电路的设计能够解决功耗、系统速度、时钟偏移等问题，成为当前VLSI研究的热点。
The design and implementation of high speed low power VLSI structure and the analysis and design of high performance on-chip interconnect are two key fields of VLSI design.
高速低功耗VLSI结构的设计实现以及片内高性能互连线的分析设计是VLSI设计的两个关键领域。
There are three physical effects on the power grid. Among them, IR-Drop effect and ground bounce effect impact the signal integrity while electro-migration impacts the reliability of VLSI design.
电源网格上存在着三种主要的物理效应，其中压降效应和地弹反射效应影响信号的完整性，电子迁移效应影响芯片设计的可靠性。
Now, the design and manufacture technology of VLSI have been perfected.
当代超大规模集成电路设计与制造技术日趋成熟。
At first, this thesis introduces the VLSI physical design process, based on this leads to the rectilinear Steiner tree problem.
本文首先介绍了超大规模集成电路的物理设计流程，在此基础上引出直角斯坦纳树问题。
These strategies based on the graph theory have theoretic and practical significance in the design of VLSI.
这些策略均以图论为基础，对VLSI布图设计具有一定的理论和实用意义。
In order to reduce the cost of developing VLSI test program and shorten developing cycle, an idea of a simulator design of test system and gives the simulators structure and function is put up.
为了降低开发超大规模集成电路器件的测试程序的费用，缩短开发周期，给出了一种设计和开发测试系统仿真器的基本思想、结构组成及其功能。
Two-layer channel routing is one of the key steps in the automatic layout design of VLSI chips.
两层通道布线问题在超大规模集成电路自动布图设计中是关键步骤之一。
VLSI partitioning is an effective method for reducing complexity of VLSI circuit design.
电路划分是降低超大规模集成电路设计复杂性的有效方法。
A computer aided simulation system CASSY (computer aided simulation system) for VLSI (Very Large Scale Integrated) circuits systems was presented to keep the design procedure of VLSI out of mistakes.
为保证超大规模集成电路(VLSI)设计过程的正确无误，本文提供了一个电路系统的计算机辅助模拟系统(CASSY)。
Facing the challenge of design scale of VLSI becoming larger, except for circuit parallel, the existing basic parallel approaches cannot solve test generation complexity problems radically.
面对VLSI设计规模日益增大的挑战，除了电路并行以外，其它已有的基本并行策略都无法从根本上解决测试生成的复杂性问题。
Packing problem is faced in many industries, for example, the container loading, the sheet cutting, the design of VLSI and the newspaper editor.
装箱问题是个在工业生产中经常碰到的问题，如集装箱的装载、板材的切割、集成电路的设计、报纸的排版等等。
The placement problem is an important problem in VLSI layout design, but results from traditional methods are not satisfied.
布局问题是VLSI布图设计中的重要问题，传统的方法很难得到满意的解答。
Semiconductor device simulation has manifested its ever-increasing importance for the design of miniature devices in VLSI end new discrete devices.
半导体器件模拟，对于设计VLSI中的微小尺寸器件或者是新型的半导体分立器件，都已越来越显得重要。
Low power design is playing a more and more important role in VLSI nowadays.
低功耗设计在当前超大规模集成电路中越来越重要。
It is important to the calculation of VLSI critical area and the optimization of IC layout design.
这对计算VL SI关键面积、指导版图优化设计和提高IC成品率有重要意义。
Under this background the dissertation is intended to develop some algorithms for VLSI physical design detailed routing.
本文正是在这样的背景下对VLSI电路物理设计中的详细布线问题展开了一些研究工作。
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