The difference clock delay match technology adjusts the two channel AD analog clock phase and implements the two way AD uniformly-space sampling.
差分时钟延迟匹配技术通过对两路AD的采样时钟进行相位调整，实现了两路AD的等间隔采样。
The switching circuitry provides the first phase current waveform during at least two offset sampling instants, and provides the second phase current waveform during a reference sampling instant.
切换电路提供在至少两个偏移采样时刻期间的第一相电流波形，且提供在参考采样时刻期间的第二相电流波 形。
When fault duration is longer than phase difference will result in fault sampling by two registers and make feedback circuit in fault state for a long time.
当故障持续时间大于三路时钟相位差时使两路时钟同时采样到故障值，在反馈型电路会导致长时间的故障状态。
In chapter 4, introducing the application of calibration estimator in two-phase sampling, non-response and sampling rotation.
第四章，从横向上介绍了校准估计量在二重抽样中的应用、在无回答中的应用，并推出其在样本轮换中的应用。
In chapter 4, introducing the application of calibration estimator in two-phase sampling, non-response and sampling rotation.
第四章，从横向上介绍了校准估计量在二重抽样中的应用、在无回答中的应用，并推出其在样本轮换中的应用。
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