Balance-tlb (transmit load balancing).
balance - tlb(传输负载平衡)。
Ship the 6.0 type library from Windows 7 RTM via the new type library file msado60.tlb.
通过新的类型库文件msado60 . tlb为Windows7RTM发布6.0类型库。
One option is to increase the TLB size.
一种选择是增加TLB大小。
This is because TLB is able to map a larger virtual memory range.
这是因为TLB能够映射更大的虚拟内存范围。
However, because of on-chip space limitations, the TLB size can not be increased proportionally.
然而，由于芯片空间的限制，TLB的大小不能成比例地增加。
The TLB miss overhead represents one important component of the overall CPI metric.
TLB失误的开销是整个CPI度量中的一个重要部分。
TLB is the cache holding the mapping information from the virtual address to the physical page in memory.
TLB缓存包含从虚拟地址到内存中物理页面的映射信息。
This research focuses on multi level set associative TLB performance of the general purpose microprocessor.
本文针对超深亚微米通用微处理器中的多级tlb设计开展研究。
The fewer pages would mean that the TLB process would have a higher hit ratio and therefore improved performance.
页数越少，意味着TLB进程将具有更高的命中率，因而性能更好。
TLB cache entry reuse (cache hit) equates to quicker address translation and subsequently faster access to physical memory.
tlb缓存条目重用(缓存命中)意味着更快的地址转换，还意味着对物理内存的更快的访问。
A TLB miss requires accessing a page table that is stored in the main memory, which consumes considerably more processor cycles.
如果TLB没有命中，那么就需要访问存储在主存中的页表，而这样做需要消耗相当多的处理器周期。
Whenever an instruction is fetched from memory, the instruction pointer is translated via the instruction TLB into a physical address.
无论何时从内存中取一个指令，指令指针都会经指令tlb的翻译后指向物理地址。
To speed up address translation, there is a processor-on-a-chip (PoC) cache and associated logic called translation lookaside buffer (TLB).
为了加快地址转换，架构中有一个 processor-on-a-chip (PoC)缓存和相关的转换后备缓冲器 (TLB)逻辑。
If you can modify the Interface Definition Language (IDL) source, you can apply type library file (TLB) attributes and import the type library.
如果可以修改接口定义语言(idl)源，就可以应用类型库文件(TLB)特性并导入类型库。
"In response to all he has done for us, let us outdo each other in being helpful and kind to each other and in doing good" (Hebrews 10:24 TLB).
为了响应他为我们做的一切，让我们彼此相顾，激发爱心、勉励行善。
To help address translation, operating systems cache the translated memory addresses by a process called Translation Look-aside Buffering (TLB).
为了帮助地址转换，操作系统通过一个叫做转换后援缓冲（Translation Look-aside Buffering，TLB） 的进程来缓存已转换的内存地址。
A new high-speed TLB architecture is designed for accelerating the address transition rate from linear address to physical one in micro processors.
为了加快微处理器中线性地址向物理地址转换的速度，提出了一种高速tlb结构。
With 16-megabyte and 16-gigabyte pages, a further improvement in TLB hit rate led to proportional CPI gains and, therefore, higher overall throughput.
当使用 16 MB和16 GB页面时，TLB 命中率进一步提高，导致CPI成比例增长，从而取得了更高的总体吞吐率。
This difference in performance gain is predictable because the pressure on the TLB cache increases as the size of the database and the memory assigned to the DB2 buffer pools increases.
这两组测试得到的性能结果的不同是可以预测的，因为随着数据库和分配给db2缓冲池的内存的增加，TLB缓存上的压力也随之增加。
In order to optimize performance, including speed and the usage of its memory, CPU usually hires a Translation Lookaside Buffer(TLB) to translate the virtual address into physical address.
为了提高CPU的速度和更有效的管理物理内存，一般都采用转换查找缓冲器（TLB）将虚拟地址转换为物理地址。
The profiling table provides the percentage and number of samples collected for specified processor events such as the number of cache line misses, Transition Lookaside Buffer (TLB) misses, and so on.
评测表提供为特定的处理器事件收集的采样的百分数或数量，比如高速缓存线路故障的数量、传输后备缓存(TLB)故障的数量，等等。
The profiling table provides the percentage and number of samples collected for specified processor events such as the number of cache line misses, Transition Lookaside Buffer (TLB) misses, and so on.
评测表提供为特定的处理器事件收集的采样的百分数或数量，比如高速缓存线路故障的数量、传输后备缓存(TLB)故障的数量，等等。
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