The concept of IP soft core is introduced.
简单介绍了IP软核的概念。
0 device controller IP soft core is introduced.
0设备控制器IP软核的设计与实现。
NIOS II is a soft core, which is in favor of designing special imbedded system.
NIOSII是一个嵌入的软核，非常有利于构建自己的专用嵌入式系统。
The parameterized design about the C8051 micro controller IP soft core is studied.
研究了C8051微控制器IP软核的参数化设计。
Revision of stress and deformations caused by the elastic supporting of the soft core.
引入夹芯弹性支撑作用对变形与应力的修正。
As a kind of IP core, IP soft core has a big advantage in reuse design because of its flexibility.
作为IP核形式之一的IP软核，灵活性高，在IP核复用中有很大优势。
This paper designed and implemented a USB host controller soft core that can be used in mobile devices.
本文的目的就是要设计并实现一个可集成在便携、移动产品上的USB主机控制器软核。
SOPC design is one of hotspots in embedded system fields. Using a mature MCU soft core is a crosscut to enter this field.
可编程片上系统(SOPC)是近期嵌入式系统设计的热点之一，利用成熟的处理器软核是进入这一领域的捷径。
The thesis construct SOPC system in FPGA based on NIOS soft core CPU to realize the image processing which only could be finished by DSP device.
本文是以Nios软核CPU为核心处理器，在FPGA中构建SOPC，实现原来主要由DSP器件才能完成的图像处理功能。
Finally, the dissertation research on the application technology of 80c51 IP soft core, and design an IP-base system used for high speed data collection.
最后，研究IP软核应用技术，设计基于80c51 IP软核的高速数据采集应用系统。
According to the design reuse methodology, this dissertation focus on the research of widely used 80c51 IP soft core, including the test and application technology.
本文基于可复用设计方法学，对用途广泛的微处理器80c51IP软核的测试方法和应用技术进行研究。
As the interface follows the solidification front of the shell metal, the areas of soft core metal showing at the barrel surface, will be patchy and not continuous.
由于结合层往往是沿着外层金属的凝固线所形成的，因此在辊身表面所呈现的此类缺陷是不连续，不规则的。
The soft core can adopt interpolation technique to process image, can make use of VHDL to design FPGA, and can also use wavelet transform to improve the arithmetic of image process.
该软核采用插值算法进行图像处理，利用硬件编程语言VHDL对FPGA进行设计，也可利用小波变换方法对图像处理算法进一步优化。
According to the requirement of the VLSI and the wide application of power electronics, IP soft core of SPWM generation system is designed. And it can be widely applied in system level chip design.
论文针对目前大规模集成电路设计要求，结合电力电子应用，设计了一个SPWM信号产生系统IP软核，该软核可广泛应用于系统级芯片设计中。
Designed the inter-frame decoding IP soft-core, including the motion vector generation module, prediction processing modules and interpolation modules.
详细设计了帧间解码IP软核，包括运动矢量生成模块、预测处理模块和插值模块。
This paper proposes a new method for embedded system designing, based on FPGA and soft-core CPU.
提出了一种基于FPGA(现场可编程门阵列)和软核cpu的嵌入式系统设计的新方法。
With the establishing of verification and test platform for SDH chip, We realize the function simulation, timing simulation and performance test of the IP soft-core.
通过建立SDH芯片验证平台和SDH芯片测试平台，实现IP软核的功能仿真、时序仿真和芯片性能测试。
This paper presents a way to generate control signals of the interface of memory using many clocks, and offers a new way for setting up the soft-core simulation platform.
文章介绍利用多时钟产生存储器接口控制信号的方法，为建立软核仿真平台提供了一个新的途径。
With the development of high speed image processing, the soft-core processing technology of image processing system has become a hotspot of research.
随着高速图像处理技术的应用领域不断扩大，对图像处理速度的要求也越来越高，当前基于软核处理器的图像处理系统成为研究的热点。
With the development of high speed image processing, the soft-core processing technology of image processing system has become a hotspot of research.
随着高速图像处理技术的应用领域不断扩大，对图像处理速度的要求也越来越高，当前基于软核处理器的图像处理系统成为研究的热点。
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