No load tap ranges should be selected to provide an adequate low-side bus voltage.
无载分接范围选择应能提供正确的低压侧母线电压。
Logic for interface to the back-side bus for accesses to the internal unified level two processor cache.
访问内部统一二级处理器缓存的后端总线接口逻辑。
Logic for interface to the back-side bus for accesses to the internal unified level two processor cache.
访问内部统一二级处理器缓存的后端总线接口逻辑。
应用推荐