We propose a second decimation algorithm for widening the range of sweep width in the AD9874 based digital receiver.
基于AD9874 芯片的数字接收机，我们提出了一种扩展数字接收机谱宽的二次抽取算法。
One of the reasons that public/private key schemes have revolutionized digital security is because the sender and receiver don't have to share a common password.
公钥与私钥方案给数字安全带来变革的原因之一是数据的发送方和接收方不必使用公共的密码。
Known as "ACES," Raytheon's advanced countermeasures electronic system consists of a radar warning receiver, digital jammer and chaff-flare dispenser.
被称为“ACES”的雷声公司先进对抗电子系统包括一部雷达告警接收机、数字干扰机和箔条-闪光弹发射器。
Instead of simply sending its public key to the receiver, the sender sends its digital certificate issued by a ca.
发送方发送由CA签发的数字证书，而不仅仅是向接收方发送其公钥。
The headend, consisting of content providers and equipment (such as the satellite receiver, encoders, and so on) needed to transmit and receive digital assets, onto the IP network.
数据转发器，包含内容提供者和用于在IP网络上传输和接收数字资产所需的设备(如卫星接收器、编码器等)。
The receiver uses the sender's corresponding public key to verify the digital signature.
接收方使用发送方的对应公钥验证数字签名。
The latest statistics on take-up of digital TV in the UK suggest that 18 million households, 89.2%, have a DTV receiver.
英国最新进行的数字电视调查结果表明，英国已有89.2%的家庭正在使用数字电视接收装置。
Digital TV is an end to end system whose signals need to be handled in digital in program collection, program production, program transmission and terminal receiver.
数字电视是一个从节目采集、节目制作、节目传输到用户端接收机都要以数字方式处理信号的端到端的系统。
The dynamic range and the sensitivity are the key characters of wideband digital EW receiver.
动态范围和灵敏度是宽带数字EW侦察接收机的关键性能指标。
Digital down - conversion (DDC) is an important technique of digitized radar receiver.
数字下变频技术是数字化雷达接收机的关键技术之一。
In this paper, the problem of optimal design of interpolation filter for all digital receiver is discussed.
本文讨论了全数字接收机中插值滤波器的优化设计问题。
Digital channelized receiver is a typical application of software radio based on polyphase filters.
数字信道化接收机是基于多相滤波的软件无线电的典型应用。
The design of interpolation filter is one of the important problems for all digital implementation of receiver.
插值滤波器的设计问题是接收机全数字化实现的核心问题之一。
In GPS receiver many digital signal processing steps must be considered in order to align the incoming signal and local signal.
在GPS接收机中，为了将本地信号和接收到的信号同步，要完成复杂的信号处理过程。
The focus of this paper is how to implement the digital IF in wireless receiver efficiently.
本文的焦点正是如何高效的实现无线通信接收系统中的数字中频部分。
Chapter two gives a simple explanation on the framework of digital TV receiver system.
第二章对数字卫星电视接收系统的整体框架做一简单说明。
A correction method of amplitude-phase imbalance for digital receiver of a monopulse radar is presented, and its application in a real radar system is introduced.
给出了单脉冲雷达数字接收机和差三通道幅相不平衡的一种校正方法，介绍了这种方法在实际雷达系统中的应用。
And the application in intermediate frequency digital receiver proves this software system's efficiency and dependability.
在中频数字接收系统中的应用验证了此软件系统的效率和可靠性。
This article introduces the structure of the digital receiver ICS554, and accomplishes the design of FFT processor based on FPGA.
本文介绍了数字接收机ics554的结构，使用其中的FPGA完成频谱分析处理器的设计工作。
At present, the wideband digital receiver has the "bottleneck" question that the high speed ADC can not match low speed DSP processing ability.
目前的宽带数字接收机又存在着高速adc与后端低速率DSP处理能力之间矛盾的“瓶颈”问题。
This paper introduces the design and analysis of software radio mind based IF digital radar receiver.
本文介绍了基于软件无线电思想的雷达中频数字化接收机的设计与性能分析。
Wide frequency spectrum can be received and high probability of intercepting can be got and the simultaneously attend signals can be processed by wide band radar EW reconnaissance digital receiver.
宽带雷达对抗侦察数字接收机具有较宽的瞬时频率覆盖特性和较高的截获概率，并能处理同时到达的多个信号。
The hardware of receiving and transmitting unit in the acoustic head contain the analog receiver and digital signal processing card.
声头内收发单元的硬件主要包括模拟接收机和数字信号处理机以及功放机。
In the design of RF receiver of the digital MRI spectrometer console, a digital demodulation and filtering algorithm is presented in this thesis.
针对数字化MRI谱仪中射频接收器，提出了一种磁共振信号的数字解调和滤波的设计方案。
In this dissertation, we mainly study the efficient architecture of channelized digital receiver, discuss the particular realization approaches, then testify them with simulation.
本文主要研究了通道化数字接收机的高效结构，讨论了具体实现方案并进行了模拟验证。
All circuits are designed by HDL and can be intergrated in one CPLD or FPGA chip, used in the frame synchronization and timing of digital communications receiver.
全部电路由硬件描述语言实现，可以集成在一片CPLD或FPGA芯片内部，用于数字通信系统接收端的帧同步和定时。
In this paper, the conception of SWR is introduced, and the structure of digital IF receiver system is discussed including its core technology.
本文介绍了软件无线电的概念，探讨了数字中频接收机系统结构及其采用的关键技术。
The real time processing of high speed data flow makes strict demands on the performance of descendant digital down converter in the wideband digital receiver.
在宽带数字接收机中，高速数据流的实时处理对后继数字下变频器性能提出了极为苛刻的要求。
The real time processing of high speed data flow makes strict demands on the performance of descendant digital down converter in the wideband digital receiver.
在宽带数字接收机中，高速数据流的实时处理对后继数字下变频器性能提出了极为苛刻的要求。
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