In order to minimize the PLL jitter, it is recommended to avoid active signal on the TEST output.
为了尽量减少抖动的锁相环，建议，以避免在测试输出的积极信号。
The phase jitter of output signal of the PLL( phase locked loop) frequency doubler is analyzed.
定量分析了数字式锁相倍频器输出信号的相位抖动。
We present a design for an adaptive gain phase-locked loop (PLL) that features fast acquisition, low jitter, and wide tuning range.
提出了一种快捕获，低抖动，宽调节范围的增益自适应锁相环的设计。
As the voltage VCTR varies, VCO 104 varies the frequency of the VCO output signal, causing phase offsets and increased output jitter when PLL 100 is in lock mode, as shown by dotted line 202.
随着电压VCTR改变，VCO 104改变VCO输出信号的频率，使得当pll 100处于锁定模式时引起脉冲偏移和增大的输出抖动，如图中虚线202所示。
Because of the merit of integrated easily, low power, low jitter, small phase difference error and big capture scale, the CPPLL (Charge-pump PLL) has become one of the major digital PLL product.
电荷泵锁相环具有易于集成、低功耗、低抖动、频率牵引范围大和静态相位误差小等优点，成为了当前数字锁相环产品的主流。
The low jitter transmission of pulse signals is realized by direct RF-modulation based on PLL frequency modulation.
介绍了锁相调频的基本原理，用锁相调频的射频直接调制方法实现了脉冲信号的低抖动传输。
The low jitter transmission of pulse signals is realized by direct RF-modulation based on PLL frequency modulation.
介绍了锁相调频的基本原理，用锁相调频的射频直接调制方法实现了脉冲信号的低抖动传输。
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