The FIFO module in FPGA was applied to realize the pixel clock modification and the data saving and taking.
采用FPGA内部集成的FIFO模块实现像素时钟的改变和图像数据的存取。
Pixel clock output frequencies range from 10mhz to 140mhz with sampling clock jitter of 250ps peak to peak.
像素时钟输出频率范围从10mhz到140mhz的采样250ps的峰峰值抖动。
Pixel clock output frequencies range from 10mhz to 140mhz with sampling clock jitter of 250ps peak to peak.
像素时钟输出频率范围从10mhz到140mhz的采样250ps的峰峰值抖动。
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