A path delay fault testing generation algorithm for digital circuits based on neural network is proposed because the testing generation for path delay fault in digital circuits is more difficult.
针对数字电路路径时滞故障测试生成较难的问题，提出了基于神经网络的数字电路路径时滞故障测试生成算法。
A path delay fault testing generation algorithm for digital circuits based on neural network is proposed because the testing generation for path delay fault in digital circuits is more difficult.
针对数字电路路径时滞故障测试生成较难的问题，提出了基于神经网络的数字电路路径时滞故障测试生成算法。
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