时钟信号总是由设备端生成的。

The device always generates the clock signal.

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其中一种方法是使用某种形式的时钟信号。

One way to do this is by using some form of clocking signal.

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时钟信号输入端被设计用于提供时钟信号。

A clock signal input is designed to supply a clock signal.

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串行时钟信号；

Serial Clock singal ;

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时钟信号和时钟偏差对电路性能的影响也越来越明显。

Clock signal and clock skew become more and more important in the circuit performance.

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我们知道，在硬件电路设计中时钟信号时非常重要的。

We know that the hardware circuit design clock signal is very important.

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之前看的那些顺序逻辑的例子好像确实全都没有时钟信号。

For sequential logic, the key is clock. Everything has to be synchronized with clock.

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这些额外的信号会让身体主时钟更晚察觉夜幕的降临。

The extra light input can push your master clock's sense of night ever later.

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首先，平常的RISC计算机是同步的，由一个时钟提供一个同步的信号。

First, the usual RISC is synchronous, supplied a clock single by a clock element.

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码型转换是实现非归零(NRZ)信号全光时钟恢复的关键技术。

Pattern conversion is the key technology for all-optical clock recovery from non-return-to-zero (NRZ) signal.

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时钟本身也是数字信号，也会干扰模拟电路。

System clock recover is the key in digital TV system.

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时钟本身也是数字信号，也会干扰模拟电路。

System clock recover is the key in digital TV system.

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