Due to the latency difference between main memory and on-chip memory cache, POWER7 was designed with three levels of on-chip cache (see Figure 1).

由于主内存和芯片级内存缓存之间的延迟差别，POWER 7设计了三种级别的芯片级缓存机制(见图1)。

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In the meantime, the module takes advantage of on-chip cache to reduce the pressure on the system buses.

同时，该设计还使用片上缓存方式，降低了系统总线的占用率。

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In the meantime, the module takes advantage of on-chip cache to reduce the pressure on the system buses.

同时，该设计还使用片上缓存方式，降低了系统总线的占用率。

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