A transition in a logic signal from a logic high to a logic low is referred to as a falling edge.
逻辑信号从高电平到低电平的转换被称为下降沿。
If the power supply voltage decreases, the state of the select signal is changed from a logic high to a logic low.
如果电源电压减小，则选择信号的状态从逻辑高改变为逻辑低。
However, according to alternative embodiments of the present invention, a pulse can refer to a period of time when a digital signal is in a logic low state.
然而，依照本发明可替换实施例，在数字信号处于逻辑低电平状态时，脉冲也可指时间周期。
It provides a framework to build device adapters for device communications, and also provides a location for business logic with low latency requirements.
它提供了一个框架来为设备通信构建设备适配器，并为面向低延迟需求的业务逻辑提供了一个位置。
Each device is also a platform for local business logic where fast response, low latency, load distribution, bandwidth conservation, and high reliability are needed.
每个设备都是一个面向本地业务逻辑的平台，需要满足快速响应、低延迟、负载分配、带宽节约和高可用性。
The results of this work show that non-planar, multi-gate device architecture is an effective way to improve the scalability of III-V QWFETs for low power logic applications,’’ according to the firm.
本文显示立体型多栅结构可有效提升低功耗逻辑用III-V族QWFET管子的尺寸缩微能力。
This also frees you from low-level data conversion and mapping tasks, and enables you to focus more on business logic development.
而且您再也不用执行低级数据转换和映射任务，使您能够更多地关注业务逻辑开发。
Therefore, the application developer need only focus on coding the business logic without having to code the low-level services automatically handled by the container.
因此，应用程序开发者只需集中精力对业务逻辑进行编码而不必对底层服务编码，这些底层服务由容器自动处理。
Applying the data access Object (DAO) pattern throughout the applications enabled us to separate low-level data access logic from business logic.
在整个应用程序中使用数据访问对象(DAO)使我们可以将底层数据访问逻辑与业务逻辑分离开来。
It allows developers to focus on writing business logic and can free them from the need to spend significant cycles on more low-level implementation techniques.
它允许开发人员集中精力编写业务逻辑，而不必将大量的时间花费在更为底层的技术实现上。
If BPEL is used, it is important that BPEL is controlling the high level steps, not being used as a visual coding language to perform low-level logic.
如果使用BPEL，重要的是BPEL要控制高级步骤，而不是被用作一种可视编码语言来执行低层逻辑。
Twitter4J wraps many functions so we can focus on our logic without touching the low-level API calls to Twitter.
Twitter 4 J封装了许多函数，所以我们可以关注逻辑，无需接触Twitter的低级别API调用。
To implement and consume REST web services, you need to focus only on the application business logic and not on the low-level technical details.
要实现和使用RESTweb服务，您只需要关注应用程序业务逻辑，而不需要关注低级技术细节。
Protection of business logic assets by shielding from low-level technology change.
通过屏蔽底层技术变更来保护业务逻辑资产。
Developers use this pattern to separate low-level data access operations from high-level business logic. A typical DAO implementation has the following components.
开发人员用这种模式将底层数据访问操作与高层业务逻辑分离开。
When magnetic logic elements are employed, high reliability, low maintenance and long working life are attained.
采用磁性逻辑元件组成的系统，能增加可靠性，减少维护及延长使用寿命。
If you chose DOUT (digital out), radio buttons LOW and HIGH appear to change its logic level.
如果你选择DOUT(数字)，单选按钮高低似乎改变其逻辑电平。
We separate the physical view and logic view of IR, and make algorithms work on the high-level logic view, and map the high-level algorithms into low-level IR through view transformations.
分离对象的物理视图与逻辑视图，隐藏物理视图的实现细节，使算法工作在高层的逻辑视图上，并通过视图变换将高层算法映射到低层中间表示上。
This paper introduces the design and realization of a high-speed and low-cost virtual logic analyzer based on FPGA and USB2.0 bus.
本文介绍了一种基于FPGA的USB2.0高速、低成本的虚拟逻辑分析仪的设计原理与实现方法。
De-multiplexed CMOS outputs allow for easy interfacing with low cost FPGAs and standard logic.
通过解复用CMOS输出，能够与低成本FPGA和标准逻辑实现轻松接口。
This dissertation detailedly investigate the symbolic logic and some typical techniques for low power FSM logic synthesis and optimization.
论文详细讨论了低功耗有限状态机综合与优化中的符号逻辑和一些典型方法。
The unit shall be equipped with control logic that shuts down all electricity to the heating elements in the event of no water or low water levels in the tank.
这种热水器应该配置控制逻辑电路，当出现无水或水位太低状况时，能够自动关闭加热元件的电源。
From the comparison, we know that MCML is most suitable for working under low voltage supply among the logic families.
通过对比发现，MCML电路比其它逻辑电路更适合在低电源电压下工作。
Level restoration pass-transistor logic is proposed for low speed cell while dynamic transmission gate logic for high speed cell.
低速单元采用带有电平恢复的传输管逻辑实现，高速单元采用动态传输门逻辑实现。
The a data is latched if le is low and clock is held at a high or low logic level.
在一个数据锁存如果LE是低，时钟是在高或低的逻辑电平举行。
To erase redundancy of the clock, improve clock utilization rate and reduce power dissipation, this paper proposes the logic design of low power flip-flop based on double edge trigger.
从消除时钟冗余，提高时钟利用率以达到降低功耗的思想出发，提出基于双边沿触发的触发器的逻辑设计。
User-defined logic can be added conveniently into SOPC design and it is the flexibility, tight coupling, high efficiency and low power consuming of user.
在SOPC设计中可方便地加入用户自定义逻辑，而用户自定义逻辑具有灵活性、紧耦合性、高效率、低功耗等特性，使SOPC设计的优越性得以充分体现。
Low cost test for integrated circuits or electrical modules using a reconfigurable logic device is described.
描述了使用可重新配置逻辑器件对集成电路或电模块的低成本测试。
Use the predominance of new programmable logic chip on digital signal domain lucubrate on the implement with FPGA of speech signal low bit rate coding.
本文利用新一代可编制逻辑器件在数字信号处理领域的优势，对语音信号低码率编码的FPGA实现进行了深入研究。
Low logic update rates such as this are common in games such as real-time strategy games, where logic can eat up a lot of time in pathfinding and AI calculations that would choke a higher rate.
在实时策略类游戏中可能会使用这样低的逻辑更新帧率，这里逻辑更新会因寻路和AI计算而占用大量的时间，在这种情况下使用高的逻辑更新帧率显然不行。
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