Typically, a pulse refers to a period of time when a digital signal is in a logic high state.
通常，在数字信号处于逻辑高电平状态时，脉冲指时间周期。
A transition in a logic signal from a logic high to a logic low is referred to as a falling edge.
逻辑信号从高电平到低电平的转换被称为下降沿。
If the power supply voltage decreases, the state of the select signal is changed from a logic high to a logic low.
如果电源电压减小，则选择信号的状态从逻辑高改变为逻辑低。
The receiver input has a fail-safe feature that guarantees a logic-high output if the input is open circuit.
接收器输入具有失效保护特性，当输入开路时，可确保逻辑高电平输出。
The receiver input has a fail-safe feature that guarantees a logic-high output if the input is open circuit.
接收器输入具有失效保护特性，当输入开路时，可确保逻辑高电平输出。
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