Many implementations of full-adder and register are contrasted and studied. The full-adder and register with the lowest power consumption are chosen.
通过对多种全加器和寄存器的实现方法进行了比较研究，选择了功耗最低的全加器和寄存器。
We take the Full Adder as an example to introduce the use of VHDL in the design of digital system, the experiment of digital circuit and the teaching.
本文以全加器为例介绍其在数字系统设计和数字电路实验及教学中的应用。
A model of algorithm has been proposed for composite neural network and the classification results of high precision are obtained through a full adder (FA) fostered by the model.
提出了一种复合神经网络的算法模型，用该模型训练全加器(FA)获得了高精度分类结果。
The ideas presented in this paper are then demonstrated on the design of an ECL 1-bit full adder.
所提出的方法已用一位全加器的设计实例予以演示。
Binary Addition and Subtraction, Implementation and Performance of the Full Adder, High-speed Addition, Signed Arithmetic.
二进制加减法，全加器实现及其性能，高速加法，带符号算术运算。
Binary Addition and Subtraction, Implementation and Performance of the Full Adder, High-speed Addition, Signed Arithmetic.
二进制加减法，全加器实现及其性能，高速加法，带符号算术运算。
应用推荐