Implement the channel out-coding based on FPGA.
完成信道外编码的FPGA实现与验证。
The acquisition controller is redesigned by applying FPGA chip.
用FPGA芯片对采集控制器重新设计。
The FPGA interface to a novel current sensing circuit is designed.
设计了新型数字化电流检测系统的FPGA接口。
For example, an add-in PCI card might use this approach to initialize an FPGA.
例如，插件pci卡可能使用此方法来初始化fpga。
The FPGA decompresses the data stream, accelerating it by up to eight times.
FPGA解压数据流，可以将速度提升高达8倍。
You've now downloaded and started your first PowerPC program inside an FPGA.
现在已经在FPGA内下载并启动了您的第一个PowerPC程序。
FPGA is regarded as DMA controller, acquisition controller and BUS controller.
把FPGA用作D MA控制器、采集控制器和总线控制器。
The loading mode and process of programmable data of FPGA device are discussed.
探讨现场可编程门阵列（FPGA）器件编程数据的装载模式及过程。
This paper mainly introduced raster displacement detection system based on FPGA.
本论文主要研究基于FPGA的光栅位移检测系统。
A design method of a driving circuit for flat panel display based on FPGA is introduced.
介绍了一种基于FPGA的平板显示器件驱动电路的设计方法。
For development purposes, you can load the FPGA directly from a host PC over a JTAG interface.
就开发目的而言，可通过JTAG接口直接从主机PC加载FPGA。
A design of video monitoring system using TDM exchanging system based on the FPGA is proposed.
提出了一种利用基于FPGA的tdm交换系统的视频监测系统设计方案。
The usual method is to include a tiny program inside a piece of block ram (BRAM) within the FPGA bitstream.
通常的方法是在fpga比特流中的一段块ram (BRAM)内包含一个小程序。
The structure of high speed infrared image acquired and pre-process system based on FPGA is presented.
介绍了基于FPGA的红外视频图像高速采集及预处理电路的总体结构。
Hardware random number generator in the FPGA interface is used to accelerate the evolutionary algorithm.
FPGA接口中的硬件随机数发生器实现进化算法的硬件加速。
You would probably not choose this method for a system where the FPGA itself is going to be the main processor.
如果系统中fpga本身将作为主处理器，则不应该为该系统选择此方法。
A general radar signal simulation, acquisition and processing system based on FPGA is designed and implemented.
介绍了基于FPGA设计并实现了一种雷达信号模拟、采集与处理的系统。
Chapter five briefly introduces the implementation of system software including DSP, FPGA and PC control Programming.
第五章介绍了系统的软件实现，包括了DSP程序，FPGA程序和主机程序。
So a digital real time system for radar signal acquisition and processing is designed by the chip of FPGA and DSP in this paper.
针对这一问题，本设计利用FPGA和DSP芯片，设计了一个数字化的雷达原始信号采集与处理的实时系统。
Finally, we realize the encrypting function based on FPGA, and test and analyse the whole encrypting performance of USB Cipher Card.
最后，基于FPGA实现了USB加密卡的加密功能，并对整体的加密处理性能进行了测试与分析。
A design scheme of high - performance data acquisition based on USB and FPGA and its hardware and software implementation are introduced.
提出了一种基于usb和FPGA的高性能数据采集设计方案并详细介绍了其软硬件实现方法。
Later, you can migrate various parts of the application into virtual "hardware" inside the FPGA, thereby freeing up CPU resources for other tasks.
随后，可将该应用程序的各部分迁移到FPGA中的虚拟“硬件”，从而释放CPU资源供其他任务使用。
You then build a final, shippable bitstream which gets burned onto your platform flash, or whatever method your design USES to configure the FPGA.
然后可以构建烧制到平台闪存的最终可发行的比特流，或者构建设计用来配置FPGA的任何方法。
In a nutshell, the principal benefit of the FPGA is unparalleled design flexibility as to where you place the border between hardware and software.
简单地说，FPGA的主要益处就是，它可在确定软、硬件的界限方面展现出空前的设计灵活性。
This article narrated the FPGA unique feature and the design flow, discussed the main point of using the FPGA design radar signal tracking device.
叙述了FPGA的结构特点和设计流程，讨论了利用FPGA设计雷达信号跟踪器的要点。
The FPGA then filters out any data not relevant to the query, streaming the remaining data back to memory for concurrent processing by the CPU core.
FPGA然后过滤掉与查询无关的数据，将剩余的数据放回内存，供 CPU 内核进行并发处理。
The idea is that you include this "halt and wait" code in the BRAM so you can configure the FPGA, then attach a debugger and download the code you want to run.
该理念是在BRAM中包含此“haltandwait”代码，这样就能配置FPGA，然后附上一个调试器并下载想要运行的代码。
This imports the peripheral, but at this stage it's just a disembodied piece of hardware floating around inside the FPGA (EDK won't let you build it like this).
这就导入了外部设备，但此阶段它只是FPGA中一个没有实质的硬件(EDK不允许像这样进行构建)。
Each P512 module offers 32 megabytes soldered, FPGA-controlled DDR2 SDRAM and an LVDS channel with a connection speed of 230 MHz and 86 megabytes per second.
每个P 512模块提供32兆比特焊接的、现场可编程门阵列控制的DDR2 SDRAM并具有230mhz和每秒86MB速度的LVDS通道。
Each P512 module offers 32 megabytes soldered, FPGA-controlled DDR2 SDRAM and an LVDS channel with a connection speed of 230 MHz and 86 megabytes per second.
每个P 512模块提供32兆比特焊接的、现场可编程门阵列控制的DDR2 SDRAM并具有230mhz和每秒86MB速度的LVDS通道。
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