A transition in a logic signal from a logic high to a logic low is referred to as a falling edge.

逻辑信号从高电平到低电平的转换被称为下降沿。

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The input signal is sampled on the falling edge of CS and the conversion is also initiated at this point.

输入信号在CS的下降沿进行采样，而转换同时在此处启动。

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The input signal is sampled on the falling edge of CONVST and the conversion is also initiated at this point.

输入信号在CONVST的下降沿进行采样，而转换同时在此处启动。

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Pulse width generator 404 generates a falling edge in VOUT a delayed period of time after the falling edge in VIN.

在VIN下降沿后的延迟时间周期中，脉冲宽度发生器404产生VOUT的下降沿。

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Thus, pulse width generator 404 generates a delay between a falling edge of VIN and a subsequent falling edge of VOUT.

因此，脉冲宽度发生器404在VIN下降沿和随后的VOUT下降沿之间产生延迟。

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Thus, pulse width generator 404 generates a delay between a falling edge of VIN and a subsequent falling edge of VOUT.

因此，脉冲宽度发生器404在VIN下降沿和随后的VOUT下降沿之间产生延迟。

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