The CPU architecture (s) to generate machine code for.
生成机器代码所需的CPU架构。
At the minimum, a platform is a combination of a CPU architecture and an operating system.
一个平台至少应该是一种CPU架构和一种操作系统的组合。
A full QEMU installation includes several binaries, each of which emulates a different CPU architecture.
完整的QEMU安装包含若干二进制文件，其中每个都模拟不同的CPU架构。
Moreover, the new CPU architecture will further extend the low power consumption and low noise characteristics of both family lines.
此外，新型CPU架构将进一步增强低功率消耗和低噪音的特性。
Since the SPU instruction set is not directly related to an existing CPU architecture, a new back end was written for both GCC and binutils.
由于SPU指令集并不与现有的CPU架构直接相关，因此我们为GCC和binutils编写了一个新的后端程序。
The file system data structures are not affected by the central processing unit (CPU) architecture.
文件系统数据结构不受中央处理器(CPU)架构的影响。
The architecture of the XMLNSC domain means that it USES significantly less CPU than the other XML domains.
xmlnsc域的体系结构意味着它比其他xml域使用显著更少的CPU。
It's a good architecture—I want to make that clear before I go any further, as it always seems like I'm picking on the CPU—because for what it does, it does it very well.
这是一个不错的架构——在下一步的讨论前我要先声明这一点，虽然似乎我一直在对CPU挑三拣四——因为对CPU工作特点而言，它做得相当好。
If mishandled, SQL Relay creates a new single-point-of-failure weak-link in an application architecture, one that consumes extra CPU cycles and introduces delays and errors in database retrieval.
如果处理不当的话，SQLRelay将在应用程序架构中引起新的单点故障弱连接，这将消耗更多CPU周期并在数据库检索中引入延迟和错误。
Its manufacturer claims that the CPU solves a critical problem in multi-core scaling and opens the door to hundreds or even thousands of cores using this new architecture.
该公司还声称他们在这款处理器中解决了多核处理器如何共同发挥效率的问题，因此在将来，百核千核都能很容易的实现。
Traditionally, a workstation's throughput depends on its bus and memory architecture, as well as its CPU speed.
传统上讲，工作站的吞吐量与其总线和存储器体系结构以及CPU的速度有关。
In a computer with the contrasting von Neumann architecture (and no CPU cache), the CPU can be either reading an instruction or reading/writing data fROM/to the memory.
在基于冯诺依曼架构的计算机中（没有CPU缓存），CPU或者从存储器中读取指令或数据，或者在存储器中写入数据。
The target architecture of hardware-software combined design consists of a CPU and some ASIC communicating over a bus.
软硬件协同设计的目标结构包括一个CPU和多个ASIC，它们通过一条总线进行通信。
We even looked at and modified the receiver system, improving the multitasking architecture to more actively use the CPU for our computational work.
我们甚至研究并修改了接收机系统，改善了多任务架构，使其更为活跃地使用CPU为我们的计算工作服务。
In a computer using the Harvard architecture, the CPU can both read an instruction and perform a data memory access at the same time, even without a cache.
在使用哈佛架构的计算机中，即使没有缓存，CPU也可以在读取指令的同时进行数据访问。
The achievements of this paper have important practical and realistic significance to computer architecture research, CPU designing, researching and teaching.
本文对体系结构研究、CPU设计、研究与教学具有一定的借鉴意义和实践意义。
The performance of parallel program is closely related to computer architecture, besides CPU, including system framework, instruction structure and access speed of storage unit.
并行程序的性能与计算机体系结构密切相关，不但取决于CPU，还与系统架构、指令结构、存储部件的存取速度等因素有关。
By employing this new architecture, Renesas aims to reduce code size by 30% and CPU power dissipation by 50%.
通过该架构，瑞萨科技旨在将代码尺寸减小30%，CPU的功率消耗减少50%。
This paper summarizes the techniques of programmability, reliability and low power for GPU, and discusses the development trend of the CPU-GPGPU heterogeneous architecture.
本文综述了针对这一体系结构现有的可编程性技术、可靠性技术和低功耗技术，并结合这些技术展望了CPU -GPGPU这种异构系统的发展趋势。
The system consists of two subsystems being in double CPU parallel architecture.
该系统由双CPU并行式结构的两个子系统构成。
We are sure that the new architecture that comes in roughly two years will get even more CPU features, if necessary.
我们相信，在新的体系结构，在大约两年的时间来将获得更多的CPU的功能，如有必要。
On the implementation of debugging system, two types of FPGA-CPU are tested, whose instruction system and architecture are widely different.
此外，设计了专用的编译软件，实现了基于不同指令系统的伪汇编程序编译，提高了调试效率。
This paper describes a synthetic RISC architecture CPU design and implementation in detail for teaching experiment.
详细介绍了用VHDL语言设计可逻辑综合的教学实验用CPU的过程。
This paper describes a synthetic RISC architecture CPU design and implementation in detail for teaching experiment.
详细介绍了用VHDL语言设计可逻辑综合的教学实验用CPU的过程。
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