Fabricated with 90-nanometer low-power CMOS technology, the 32-bit PowerPC e300-based multimedia SoC is clockable up to 400MHz.
这个基于PowerPCe300的32位多媒体SoC采用90纳米的低功耗CMOS技术制程，时钟频率400MHz。
SONOS flash memory has numerous advantages, such as excellent salability, high endurance, low power, radiation hardness, and is highly compatible with standard CMOS technologies.
SONOS闪存拥有许多优势，如极好的销路、高持久性、低动力支持、辐射硬度和拥有标准CMOS技术的高压缩性。
A new low-voltage low-power CMOS voltage reference operating in subthreshold region is presented.
提出了一种新型的低电压、低功耗、工作在亚阈值区的基准电压源。
A sensitive, stable and low power consumption magnetic sensor is constructed using a CMOS multivibrator circuit, in which a sharp pulse train current is applied to the treated amorphous ribbon.
同时利用CMOS多谐振荡电路产生窄脉冲电流序列对前面处理过的非晶带进行激励，制作成灵敏度高、稳定性好、功耗低的弱磁场传感器。
The controller combines parallel amplification and drain modulation of the CMOS class-E power amplifier to provide high efficiency over a broad range of output powers.
结合射频E类功率放大器的结构特点，采用CMOS工艺，达到了在大的输出功率范围内保持持续稳定高效率的目的。
A design approach for low power CMOS low noise amplifier (LNA) is presented and it is compared with the traditional LNA design method.
针对低功耗电路设计的需求，提出了一种低功耗约束下CMOS低噪声放大器的设计方法，并与传统的设计方法进行了对比。
The paper focuses on circuit design of power switch with bipolar technology and audio amplifier with CMOS techn.
本文论述双极型功率开关电路和CMOS音频功率放大器电路设计。
Three common power bus ESD protection structures in CMOS IC were discussed, the circuit structure and working theories were analyzed, an improved power bus ESD protection structure was put forward.
讨论了三种常见的CMOS集成电路电源总线esd保护结构，分析了其电路结构、工作原理和存在的问题，进而提出了一种改进的ESD保护电源总线拓扑结构。
CMOS switch which can work in ultra low power supply is designed.
设计一种能够工作在超低电源电压下的CMOS开关。
CMOS imaging sensor fits in with the requirement of applications of space technology for its advantages in power, integration and radiation.
在空间技术应用领域，CMOS图像传感器由于具有集成度高、抗辐射能力强、功率低等优势，正得到越来越多的应用；
Key challenges on CMOS scaling down into nanometer regime are discussed, such as power supply and threshold voltage, short-channel effect, quantum effect, random doping distribution and wire delay.
本论文着重论述未来CMOS进入纳米尺寸的关键挑战，如：电源电压和阈值电压减小、短沟效应、量子效应、杂质数起伏以及互连线延迟等影响。
CMOS bandgap reference (BGR) without a resistor, with a high power supply rejection ratio and output below 1v is proposed.
提出一种输出低于1V的、无电阻高电源抑制比的CMOS带隙基准源(BGR)。
Welding machine control unit is equiped with no power source arc start unit, CMOS, and high power switch.
该焊机采用“无源引弧器”引弧，引入CMOS、时基、大功率开关等集成电路进行弧焊自动控制。
Integrated circuit of a class-D audio power amplifier with very high efficiency using CMOS technology is presented in this paper.
分析了高频开关电源的特点及将其应用到音频功率放大器中所遇到的主要问题，以及解决这些问题的基本方法。
A low power design in system level using current steering architecture, which can be applied to the system of CMOS mixed signal circuit widely, is presented.
提出了一种系统级电流使能控制结构，可广泛地应用在CMOS数模混合电路中，用于实现系统级的低功耗设计。
In this paper, design technologies of sub-micron CMOS gate array, such as building library, testability, clock design, power-ground design, architecture optimizing, margin design, are presented.
本文主要论述亚微米cmos门阵列的设计技术，包括建库技术，可测性设计技术、时钟设计技术、电源、地设计技术、电路结构优化、余量设计技术等，最后给出了应用实例。
The paper designs a low voltage, micro power CMOS operational amplifier with rail-to-rail output.
完成了一个低压微功耗CMOS轨至轨输出运算放大器的研究设计。
This paper concentrates on using gated-clock in low-power design of CMOS circuits.
阐述了如何运用门控时钟来进行CMOS电路的低功耗设计。
A high-precision CMOS current reference circuit is proposed for using in low-dropout (LDO) voltage regulators with low power.
设计了一种新型的用于低功耗LDO线性稳压器的CMOS高精度参考电流源。
On the basis of other Current Conveyors' design, a new low-voltage and low-power CMOS Current Conveyor is proposed and simulated.
在深入分析其它电流传送器的基础上提出了一种新型的低电压、低功耗CMOS电流传送器电路。
A low power CMOS bandgap voltage reference source with a start-up circuit is presented based on the bandgap voltage theory.
运用带隙基准的原理，提出了一种带启动电路的低功耗带隙基准电压源电路。
A low power CMOS buffer amplifier for LCD driver is presented in this paper.
设计了一种用于LCD驱动的低功耗CMOS缓冲放大器。
Low power fast CMOS analog switch. Double pole, single throw (DPST).
低功耗快速CMOS模拟开关。双单刀单掷(DPST)。
It achieves by CMOS technics which has advantage of high integration degree and low power waste.
它采用具有的高集成度、低功耗等优点的CMOS工艺实现。
The power leakage principle of CMOS device is introduced, which is in direct portion to Hamming distance processed in gate.
文章首先简单分析了CMOS器件工作时产生功耗泄漏的机理，即与门电路内处理数据的汉明距离成正比；
Introduction was made to the composition and working principle of a power-off time delay relay which adopts CMOS digital circuit, digital dial disc for switch setting and without auxiliary power.
介绍了一种采用CMOS数字电路、数字拨盘开关整定、无辅助电源的断电延时继电器的组成及工作原理。
Adopted importable and military IC, controlled CMOS chip of switch power is of stability, reliability and long operative life.
开关电源控制芯片采用进口军用级集成电路，稳定可靠，使用寿命长。
The low power consumption is obtained by using CMOS complementary logic.
CMOS互补逻辑结构降低了电路的功耗。
In the paper authors present a new approach of speeding up power estimation of CMOS sequential circuits by circuit simplication.
文章提出了一种采用电路化简加速功耗估计的方法。
In the paper authors present a new approach of speeding up power estimation of CMOS sequential circuits by circuit simplication.
文章提出了一种采用电路化简加速功耗估计的方法。
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