It is called a shift register because the data is shifted through the register by one bit position on each clock pulse.
这就是移位寄存器，因为数据在每一个时钟脉冲的作用下通过寄存器会移动一位。
According to the logic chip design feature, the chip work's time signal can be divided into 4 kinds: clock signal, input signal, combination output signal and register output signal.
按照逻辑芯片设计特点，将芯片工作时的信号分为4种：时钟信号、输入信号、组合输出信号和寄存器输出信号。
The models studied in this paper include linear shift register sequences, feedforward sequences and clock controlled sequences.
本文研究的模型包括线性移位寄存器序列，前馈序列和钟控序列。
The protocol realized some functions, such as two-way data buffer, shift register, clock circuit and parity check.
在通信协议中，主要实现了双向数据缓冲器、数据移位寄存器、时钟控制电路以及奇偶校验等功能。
The parallel loading of the flip-flop can be synchronous (i. e., occurs with the clock pulse) or asynchronous (independent of the clock pulse) depending on the design of the shift register.
触发器的并行加载可以是同步的(即在时钟脉冲到达时发生)或异步的(不依赖于时钟)，这取决于移位寄存器的设计。
Frequency controlled data (m) plus an accumulative phase data output by a phase register in an N-bit adder when a clock pulse comes, the result is sent to the input port of the phase register.
每来一个时钟脉冲，N位加法器将频率控制数据m与相位寄存器输出的累加相位数据相加，并将结果送相位寄存器输入端。
Each cell contains a register. Each register successively acquires logic calculation results in synchronization with a clock and maintains them.
在各单元中包括寄存器，各寄存器与时钟脉冲同步，依次取得逻辑运算结果并加以保存。
The project includes two outdoor learning Spaces. One of the Spaces surrounds a 'rain clock' which is a dry retention structure that adjusts seasonally to spatially register storm - water.
该项目包括两个室外学习空间，其中一个围绕“雨水时钟”设置，“雨水时钟”是一种干式持水结构，可以进行季节性调整以容纳雨水。
The project includes two outdoor learning Spaces. One of the Spaces surrounds a 'rain clock' which is a dry retention structure that adjusts seasonally to spatially register storm - water.
该项目包括两个室外学习空间，其中一个围绕“雨水时钟”设置，“雨水时钟”是一种干式持水结构，可以进行季节性调整以容纳雨水。
应用推荐