This paper introduces a method for intelligent clock design with 89c2051.
本文介绍了用89c 2051实现智能闹钟的设计方法。
The system is of double clock design structure which makes the odd verifying circuit structure simple and easily effected.
系统采用双时钟设计结构，使得奇校验电路结构简单、易实现。
This paper mainly analyzes the application of the IBIS model in the system board design and system clock design for mobile computers.
本文主要分析了IBIS模型在移动微机板参设计和在系统时钟设计中的应用。
Combining the Constructivism Ideology and taking the case of digital clock design, this paper presents the Application of Constructivism Ideology in Embedded System course teaching.
结合嵌入式系统课程的特点，并以数字时钟的设计为例，介绍了将建构主义教学理论应用于嵌入式系统课程教学。
In this paper, design technologies of sub-micron CMOS gate array, such as building library, testability, clock design, power-ground design, architecture optimizing, margin design, are presented.
本文主要论述亚微米cmos门阵列的设计技术，包括建库技术，可测性设计技术、时钟设计技术、电源、地设计技术、电路结构优化、余量设计技术等，最后给出了应用实例。
Its first design was very simple and all instructions were completed in one clock cycle.
它的第一个设计非常简单，所有指令都在一个时钟周期内完成。
But Toyota and teams of suppliers in the company's supply-chain network worked round the clock for days to design and set up alternative production sites.
但是丰田和它的供应商团队连续工作了几天几夜，设计并建立了替代的生产基地。
They had been working round the clock for a couple of days hoping to get the design out before their competitors did.
他们昼夜不停地干了几天，希望先于竞争者把设计搞出来。
Gallium arsenide switches ten times faster than silicon all of a sudden, I've got a clock speed ten times faster with no change in design.
砷化镓启动的速度是硅的10倍，突然，我得到了10倍快的时钟速度，但是设计没有发生任何改变。
Under the metro design there is no clock, taskbar, or notification tray.
在Metro设计下，界面上没有时钟，没有任务栏，没有通知区。
It is also a practical bed, because you can use the unusual design to store certain objects, such as an alarm clock or a book.
它也是一张实用的床，你可以利用其独特的设计来存放特定物品，如闹钟或书籍之类。
They didn’t improve the clock speed, presumably to keep manufacturing design costs low and to keep battery performance at parity with the first model.
他们并没有提升处理器频率，应该是为了保持硬件设计低成本和与一代相同的电力表现。
In design of pulsed asynchronous sequential circuits, it will solve for equations of clock and equations of state, on a symbolic Karnaugh map.
在异步时序电路设计中，它将时钟方程和状态方程的求解归在统一的符号卡诺图上进行。
The article introduces a design method of a general serial interface clock chip.
介绍了一种通用串行接口时钟芯片的设计方法。
According to the logic chip design feature, the chip work's time signal can be divided into 4 kinds: clock signal, input signal, combination output signal and register output signal.
按照逻辑芯片设计特点，将芯片工作时的信号分为4种：时钟信号、输入信号、组合输出信号和寄存器输出信号。
The paper introduces the design of digital clock based on FPGA and VHDL, the time of clock can be displayed with the digital driving circuit.
介绍了利用VHDL硬件描述语言结合FPGA可编程器件进行数字钟的设计，并通过数码管驱动电路动态显示计时结果。
Low-power oriented design techniques include selecting low-power parts, low operation voltage, managing clock of MCU or making MCU turn into dormancy, managing power supply of circuit and so on.
低功耗设计的关键技术包括选用低功耗的各类器件，低工作电压，对MCU进行时钟管理或休眠，对各部分电路和器件进行电源管理等。
The design and application of the PC card of GPS based synchronous clock were introduced.
介绍了基于GPS的时钟同步pc卡的设计与应用。
Clock skew is in a synchronization digital integrated circuit design difficult problem.
时钟偏移是同步数字集成电路设计中的一个难题。
The VCO module makes use of differential coefficient circuit design technology to lower the effect of power resource on the clock signal input shake.
系统VCO模块采用微分电路设计技术，可将电源噪音对时钟信号输出抖动的影响降至最低。
It emphasized the programming thoughts of data collection, display, storage, clock control and RS485 communication in software design.
着重阐述了软件设计中数据采集、显示、存储、时钟控制、RS485通信的编程思路。
We know that the hardware circuit design clock signal is the most important one of the signals.
我们知道，在硬件电路设计中时钟信号是最重要的信号之一。
The system uses clock temperature chip DS18B20, the attemperation and the design.
系统采用时钟温度芯片DS18B20，调节温度的及其设计。
In this paper, multi-function digital clock system design.
本文介绍了多功能数字钟的系统设计。
In designing synchronous digital integrated circuits, the design of clock tree is an important component, which may greatly affect the performance and reliability of the system.
时钟树的设计是同步数字集成电路设计中的一个重要部分，对系统的性能和可靠性有很大影响。
Scan Array can also benefit the design of multiple clock domains and the optimization of connectivity.
同时扫描阵列结构也为多时钟域设计以及互连优化提供了方便。
We know that the hardware circuit design clock signal is very important.
我们知道，在硬件电路设计中时钟信号时非常重要的。
In real time control system, it is important to design the clock control circuit and program.
在实时控制系统中，时钟控制电路及程序的设计十分重要。
A design method for low power clock network is proposed.
提出了低功耗的时钟网络设计方法。
A design method for low power clock network is proposed.
提出了低功耗的时钟网络设计方法。
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