Samsung Electronics, a global leader in semiconductor and telecommunication has developed a 4gb multi-chip package (MCP) targeted at 3g mobile phones market.
三星电子公司，是全球领先的半导体和电信制定了一个4gb的多芯片封装(MCP)针对3g手机市场。
Power consumption not only affects chip package type and cost, also causes the increase of chip temperature, which will decide the reliability of chip directly.
功耗不但直接影响芯片的封装形式与成本，而且过高的功耗将导致芯片温度的增加，直接决定着芯片的可靠性。
The simulation value of solder joint thermal fatigue life is 1 052 circulations. The thermal fatigue life of solder joint in SCSP is lower than the single chip package (2 656 circulations).
SCSP的焊点热疲劳寿命模拟值为1 052个循环周，低于单芯片封装元件的焊点热疲劳寿命(2 656个循环周)。
LED is the heart of a semiconductor chip, the chip is attached to one end of a stent, is the negative side, the other end of the power of the cathode, the entire chip package to be epoxy resin.
LED的心脏是一个半导体的晶片，晶片的一端附在一个支架上，一端是负极，另一端连接电源的正极，使整个晶片被环氧树脂封装起来。
Wozniak was the hardware genius, the chip-head engineer, but Jobs understood the whole package.
沃兹尼亚克是一位硬件天才，一个芯片工程师。但乔布斯了解所有的事情。
Their working model is a shoebox-sized package of electronics and liquid-filled tubes, with a silicon chip at its core.
他们的工作模型是一个鞋盒大小的电子盒和一个填满液体的管道，这个模型的核心是一块硅片。
Only when Intel's Wi-Fi chip came up to scratch did laptop-makers opt for the whole Centrino package.
只是当英特尔的WiFi芯片达到满意的性能时，膝上型电脑制造商们才开始选择整个迅驰套装。
Samsung Electronics announced that it has developed the industry's first thermally-enhanced chip-on-film (TECOF) package for the display driver IC (DDI) used in large-screen, high-resolution LCD TVs.
三星电子最近宣布，他们发明出了工业界第一个TECOF装置，这能用于大屏幕、高分辨率的LCD电视中的显示器驱动器集成电路（DDI）。
Figure 7 shows the sequence for tape bonding the chip and assembling the package.
图7所示为带状引线连接芯片和管壳装配的工艺程序。
In microelectronics, the process of connecting wires from the leads on the package to the bonding pads on the chip. Part of the assembly process.
在微电子中，使用电线将数据包的引线与芯片上的结合区相连接的过程。装配过程的一部分。
Otherwise, because it's high efficiency, the temperature above chip will not very high, we can use smaller Package scheme, this will help to the miniaturization of portable device.
另外由于其高效率，芯片发热量比较小，在封装时可以采用面积比较小的封装方案，这也有助于便携式系统的小型化。
In this paper, the merits and demerits, the key technology, the recent development and the developmental prospects for chip stacking and package stacking are introduced.
文章介绍了芯片堆叠和封装堆叠的优缺点、关键技术、最新动态和发展前景。
Introduced the package technology and technical standards for management of chip components and devices.
介绍了片式元器件的先进包装技术以及管理上所采用的技术标准。
Semiconductor device, semiconductor wafer, chip size package, and methods of manufacturing and inspection therefor.
半导体器件，半导体晶片，芯片尺寸封装及制作和检测方法。
They can be classified into wafer level, chip level, and package level stacking.
它们可以分为圆片级封装、芯片级封装、和封装面。
Quad Flat No-lead(QFN)package of microwave chip is a relatively new packaging. It offers a small size and especially fits for high density printed circuit assembly.
QFN封装的微波芯片采用一种较新的封装形式，这种封装体积很小，特别适合高密度印刷电路板组装。
This wafer level chip size package (WL-CSP) process encases the die in a solid die-size glass shell.
圆片级芯片尺寸封装（WL-CSP）工艺是在固态芯片尺寸玻璃外壳中装入芯片。
Discussed are the crucial components for the performance of this LED package as the underlying chip technology, the suitable package design and the fitting primary optics.
讨论与此种LED封装性能密切相关的议题：基础的芯片技术、合适的的封装设计和初级光学元件。
The part is available in a 32-lead lead frame chip scale package (LFCSP), and a 25-ball wafer level chip scale package (WLCSP).
该器件提供两种封装：32引脚架构芯片级封装（LFCSP）和25引脚晶圆级芯片规模封装（WLCSP）。
Moreover, some major processes package of MEMS, including wafer-level packaging, single-chip packaging, multi-chip packaging and stacked 3d packaging, etc were discussed.
阐述了MEMS的主要封装工艺和技术，包括圆片级封装、单芯片封装、多芯片组件和3d堆叠式封装等。
Picture: Latest chip and package technology for the mid-range power class.
图片：最新的芯片和封装技术为中档功率等级。
The package includes a chip carrier which has a metal substrate.
所述封装包括有金属基片的芯片支座。
Chip scale package (CSP) for flip-chip on hard substrates and wafer re-distribution is studied, and its process flow is described.
对刚性基板倒装式和晶圆再分布式两种结构的芯片级封装（CSP）进行了研究，描述了CSP的工艺流程；
The material of oar shape chemistry that phosphor turns indium chip to call photoetching glue through a kind on product line has package.
磷化铟晶片在出产线上经过一种称为光刻胶的浆状化学物质进行包裹。
Low power chip integrated package, light strip can be connected in series or parallel, no dark.
小功率芯片集成封装，灯条之间可进行串联或并联，点亮后灯条之间无暗区。
This paper talks about the major supporting technologies for MCM package: the Interlinkage of Chips, Flip Chip Bonding, Flip Bonding.
本论文研究了MCM中芯片安装互连、芯片倒装焊接及其关键支撑技术等内容。
A package for mounting an integrated circuit chip to a circuit board or the like is provided.
提供在电路板等上安装集成电路芯片的封装。
This paper describes the internal circuit of the DIP-CIB module, semiconductor chip technologies, package technologies and general purpose inverter design by using HVIC and the DIP-CIB module.
在此详细介绍了DIP -CIB模块的内部电路、半导体硅片技术、封装技术，以及如何配合专用的HVIC来实现通用变频器的小型化设计。
This paper describes the internal circuit of the DIP-CIB module, semiconductor chip technologies, package technologies and general purpose inverter design by using HVIC and the DIP-CIB module.
在此详细介绍了DIP -CIB模块的内部电路、半导体硅片技术、封装技术，以及如何配合专用的HVIC来实现通用变频器的小型化设计。
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