PROCESSOR_ARCHITECTURE: Lists the processor's chip architecture.
列出了处理器的芯片架构。
And because the chip architecture is only simulated, there is no need to obtain a license from Intel.
而芯片的构架只是模仿Intel，所以不用取得Intel的许可。
This section USES P750 and P780 systems as examples when discussing POWER7 chip architecture and capabilities.
这一节使用P 750和P 780系统作为示例来讨论POWER 7芯片架构和功能。
The company boasts a “3D chip architecture” that is called Spacetime, with “time” being the third dimension of the 3D architecture. Heady stuff.
Tabula有一款名为“Spacetime（时空）”的“三维芯片框架”，而第三维就是“时间”。
This article focuses on how to install and configure Red Hat Enterprise Linux 4 on IBM rack servers, especially those based on x86 chip architecture.
本文重点介绍如何在ibm机架服务器上安装和配置RedHatEnterpriseLinux4，尤其是在基于x86芯片架构的服务器上。
On the aspect of chip architecture, considering the factors such as parallelizable of hardware, utilization of memory and chip area, we embodied 9 scan engines on chip to realize the multi-scan.
在芯片的架构方面，考虑到硬件的可并行性，存储器资源的利用率以及芯片面积等诸多因素，我们在片内集成了9个扫描匹配引擎，来实现多线程并行扫描。
The data rate of this initial chip is 2.5 gigabits per second; the architecture supports a rate of 10 gigabits per second.
首批芯片的数据率为2.5吉比特每秒；该架构支持10吉比特每秒的速率。
Think about the loosely-coupled architecture being scaled down to the chip level.
可将其看作松耦合架构按比例缩小至芯片级。
Another architecture, that JW sees coming in the next 10 years is the one where "the network connecting enterprise resources to the cloud is a bus on a single chip."
JW认为下一个十年将会兴起的另一个架构是，连接企业资源到云的网络是一个单芯片上的总线。
Dell has produced a workstation in its Precision line that USES the Nvidia GPU chip, and a number of other vendors are producing systems based on Nvidia's parallel computing architecture.
戴尔已经生产出了使用Nvidia图形处理芯片的Precision工作站，其它的供应商也在生产基于这种并行架构的系统。
In addition, chipmakers including Samsung, Toshiba (6104.T), and Nvidia (NVDA.O) license ARM's architecture and then pay aroyalty, averaging about 10 cents, on each chip shipped.
另外，包括三星、东芝（06104.T）和Nvidia（NVDA.O）在内的芯片制造商都获得了ARM架构的生产许可，制造商每销售一片芯片就要向ARM支付大约10美分的版税。
The processor in the eye pressure monitor is the third generation of the researchers' Phoenix chip, which uses a unique architecture and an extreme sleep mode to achieve ultra-low power consumption.
眼压监测器的处理器是研究人员开发的第三代“凤凰”芯片，借助其独特的系统构架和特殊的睡眠模式，可达到超低功耗。
This paper advance the way of applying the high-end embedded microprocessor chip of AT91RM9200 into the ECG monitor, and design the ECG data acquisition system based on ARM architecture.
本文提出了将高端ARM处理器芯片AT 91rm 9200应用到心电监护仪中，设计了基于ARM体系结构的心电数据采集系统。
Structure and work principle of SDRAM chip (MT48LC16M16A2TG-75IT) is analyzed. Internal architecture and workflow of SDRAM controller is confirmed. Furthermore, its control and data path is designed.
分析了SDRAM芯片(MT 48lc16 M 16a2tg- 75it)的结构和工作原理，确定了内存sdram控制器的内部结构和工作流程，完成了内存sdram控制器的控制通路和数据通路设计。
A kind of reorganizable architecture for programmable encryption chip has been proposed in this paper.
提出了一种适用于可编程加密芯片的可重组体系结构。
It is proved in the experiments that the improved architecture not only guarantees the velocity of FFT butterfly but also economizes the chip resources and ADAPTS to FFT chip design.
实验证明，这种改进结构既保证了蝶形运算的速度，又节约了芯片资源，适合在FFT芯片设计中使用。
We put forward a technology named fixed instruction multiple data in order to accelerate the loop, and design a chip-multiprocessors architecture.
为加速循环程序执行，提出了固定指令多数据流计算模型，并设计了一个单芯片阵列处理器体系结构。
Because the CMOS chip is intended to perform all these functions, its architecture is more similar to that of an RAM chip than that of a simple image acquisition chip.
由于CMOS芯片预定用于执行所有这些功能，其类似于RAM芯片的结构胜过类似简单的图像采集芯片结构。
Network on Chip (NoC) is an emerging IC architecture that cope with the increasing complexity and communication requirements of current System on Chip (SoC).
片上网络作为一种全新的集成电路体系结构，可以很好的解决随着复杂度的增加所带来的片上通信需求问题。
The chip USES a reconfigurable architecture and very long instruction words (VLIW) to optimize the complex functions.
芯片使用可重构体系结构和超长指令字(VLIW)，优化了高复杂度函数。
The operating principle and architecture of both hardware and software of the single chip computer based intelligent instrument for this purpose are presented in this paper.
本文主要介绍了一种基于单片机的智能型保护接地电路连续性测试仪的工作原理、硬件和软件的结构。
The new chip is a new architecture, but with some basic concepts taken from the RV770, that is why the chip will be significantly faster than anything based on the RV770.
这种新型芯片是一种新的架构，但一些基本概念取自rv770，这就是为什么芯片将大大快于任何基于RV770。
The design of SOC usually adopts hierarchical on-chip-bus architecture, different IPs are integrated on different types of buses.
SOC设计通常采用层次化片上总线体系结构，不同的IP集成在不同类型的总线上。
Based on a direct-conversion architecture, the receiver integrates LNA, I/Q mixer, DC-offset removal filter, baseband amplifier and channel-select filters on a single chip.
基于直接下变频的系统架构，接收机集成了低噪声放大器、I/Q下变频器、去直流偏移滤波器、基带放大器和信道选择滤波器。
Following the lead of researchers at universities and laboratories across the US, commercial chip designers now take a quantitative approach to computer architecture.
在美国各地大学和实验室研究者们的领导下，商业的芯片设计者如今将定量方法引进到计算机结构体系之中。
Compared with foreign reference design, this architecture to shorten the processing time and the data copying times, greatly reducing host spending, easy to chip physical implementation.
与国外参考设计相比，该系统架构缩短了协议处理的时间和数据拷贝，大大降低主机的系统开销，便于芯片物理实现。
The controller system architecture consists of a S3C2410 chip with the ARM9 core running RT-Linux. The implementation including hardware and software is illustrated by a robot walking example.
使用ARM9处理器s3c 2410和RT - Linux构建小型拟人机器人控制器的系统架构，以拟人机器人的行走控制为例，从硬件和软件上介绍了控制器的实现方法。
The convolution computation can be implemented efficiently using the systolic architecture systems which are consisted of several single-chip processors served as processing elements.
由单片机作为处理单元的搏动型结构，可有效地实现卷积计算。
The convolution computation can be implemented efficiently using the systolic architecture systems which are consisted of several single-chip processors served as processing elements.
由单片机作为处理单元的搏动型结构，可有效地实现卷积计算。
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