在清单6中，从根据计数器作为初始步骤的动态sql快照数据中，您可以从总体成本、频率和每次调用成本角度列出最优sql语句。
From dynamic SQL snapshot data as the initial step based on the counters in Listing 6, you should be able to list out the top SQL statements in terms of total cost, frequency, and cost per invocation.
简单的特征频率计数器，但为什么不计数发生在实时？
Simple character frequency counter, but why won't the count happen in realtime?
该方法将GPS作为频率基准，间接得到了铷钟相对于与GPS的频差，避免了使用昂贵的高分辨计数器。
In the method, GPS is looked on as reference and the frequency difference between the Rb clock and GPS may be obtained indirectly, and the expensive high-resolution counter may not be needed.
复用开关的一个简单例子就是将单台设备的输出连接到2台仪器，例如一台伏特表和一台频率计数器。
One example of a multiple closure would be to route a single device output to two instruments, such as a voltmeter and a frequency counter.
通过计数器计数给药前后心肌细胞搏动频率的变化。
The changes of the myocardial beat frequency before and after administration were counted.
本文介绍了一种同步测周期计数器的设计，并基于该计数器设计了一个高精度的数字频率计。
The design of a counter measuring synchronous period is introduced in this paper. And based on it, a high precision digital cymometer is designed.
介绍了双计数器多周期同步法频率测量原理，给出了用单片机实现的具体实现方案。
The paper introduces the principle of frequency measure based on double-counter and multi-periods pulse synchronization method, and the designing with microprocessor is offered.
基于可编程序控制器（PLC）的水轮机调速器，受PLC内部高速计数器最高计数频率的限制，频率测量大多通过PLC外部单元来实现。
Owing to the limited frequency of the internal high-speed counter of PLC, the peripheral unit of PLC is used for PLC-based frequency measurement of hydraulic turbine governors.
假设高信号使能，计数器每个时钟周期进行计数，PWM输出的频率为时钟频率的2次幂分频。
Suppose that Enable is high, the counter counts up every clock cycle, and the frequency of the PWM output is the clock frequency divided by 2 count bits.
数控分频器设计：对于一个加法计数器，装载不同的计数初始值时，会有不同频率的溢出输出信号。
Nc divider design: an adder counter, loading the initial count value, have different frequency output signal of the overflow.
计数器的频率不能改变，而在系统运行。
在5315B频率计数器有一个100MHz的频率范围，也有比例，总计测量能力。
The 5315B Frequency Counter has a 100MHz frequency range and also has ratio and totalize measurement capabilities.
FPGA的输出是固定频率、计数器和数字比较器使占空比可变的典型波形(表1)。
The output of the FPGA is typically a waveform with a fixed-frequency, variable-duty cycle, which a counter and a digital comparator generate (Listing 1).
FPGA的输出是固定频率、计数器和数字比较器使占空比可变的典型波形(表1)。
The output of the FPGA is typically a waveform with a fixed-frequency, variable-duty cycle, which a counter and a digital comparator generate (Listing 1).
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