设计了二进制树型拓扑结构传播统一的系统时钟和触发信号，采用CPLD提供传感器间的精确时序和同步。
A binary tree routing topology is designed for propagating the system clock and trigger signal and the accurate timing and synchronization between sensors are provided by CPLD.
在数字电路中，数字频率计属于时序电路，它主要由具有记忆功能的触发器构成。
In the digital circuit, the digital frequency meter belongs to the sequence circuit, it mainly by has the memory function trigger constitution.
面向逻辑级描述的同步时序电路，以触发器为核的电路划分算法BWFSF将电路划分为大功能块。
BWFSF algorithm partition synchronous sequential circuit to many big function blocks by backward width-first search with fli.
从介绍触发器广义特性方程入手，阐述了应用它分析异步时序电路的原理和方法，并举例说明了应用。
The start from introduction of the general characteristic formula of trigger, and explains the theory and methods on analyzing as-synchronized sequential circuit. Examples are also given.
文中主要讨论常用时序逻辑模型(D锁存器、D触发器和T触发器)的建立。
This article mainly discusses the building of such sequence logic models as D_latch, D_FF and T_FF.
这些方法对于正确使用触发器和设计时序逻辑电路有重要应用参考价值。
The methods have useful reference value to using correctly flip-flops and designing sequential logic circuits.
本文利用四值逻辑讨论了触发器的逻辑功能，并讨论四值逻辑在脉冲异步时序逻辑网络分析和设计中的应用。
This paper has discussed the logic behaviour of flip-flops using the four valued logic and its applications in the analysis and design of pulsed asynchronous sequential logical networks.
本文根据电路中采用的触发器的不同敏感沿，提出采用组合时钟的异步时序电路的设计和分析方法。
According to different sensitive transitions of flip-flops used in sequential circuits, design and analysis methods for asynchronous sequential circuits are proposed by using the combinatorial clock.
通过设计实例表明，基于触发器次态方程设计同步时序电路具有一定的优点和实用意义。
Some design examples show that the design of synchronous sequential circuits based on next state equations of flip-flops is of great advantage and practical significance.
介绍了32路扫描A/D模块设计及触发模块设计和扫描时序发生器设计。
The 32 channel isolated scan A/D module is also discussed in the thesis, including trigger module and time se.
该方法之关键在于直接从时序电路的状态转换图（STD）获得J-K、D和T触发器的激励方程式。
The crux of this method is that excitation equations for J K, D and T flip flops are obtained directly from the state transition diagrams(STDs).
导出了DT触发器的激励表，提出了应用DT触发器的时序逻辑电路的设计方法，并给出了设计实例。
In this paper, DT flip - flop excitation table is developed, the design method of sequential logic circuits using DT flip - flop is presented, and the design example using the method is given.
设计了基于内部总线的同步周期触发，定义了一致的传感器、执行器单元执行时序，以及精确光纤链路数据传输模型，确保测控的高同步性。
Design of synchronous cycle trig based on internal bus, consensus definition of sensor sampling and actuator timing and precise data transmission model ensured the synchronization performance.
从介绍触发器广义特性方程入手，阐述了应用它分析异步时序电路的原理和方法，并举例说明了应用。
The start from introduction of the general characteristic formula of trigger, and explains the theory and methods on analyzing as-synchronized sequential circuit.
本文提出三值触发器串接时序电路，用实例阐述综合方法。
The sequential circuit with ternary. flip-flops in series is proposed. The synthesis for the above circuit is discussed with an example.
文章还介绍了该双边沿触发器在时序电路中的应用。
The application of this type of double-edge-triggered flip-flop in seq…
文章还介绍了该双边沿触发器在时序电路中的应用。
The application of this type of double-edge-triggered flip-flop in seq…
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