并使用时钟测试来减少生成测试向量所需的时间。
It can reduce the time used to generate the test vectors by using the clock test.
最后介绍如何编写项目所采用的受约束的随机测试向量。
Also introduce how test vectors were generated based on constraints.
该方法利用了测试向量之间的相容性，降低测试应用时间。
The proposed method USES the compatibility between test vectors to reduce test application time.
实验证明。它能以较少的测试向量对检测出比较多的故障。
Experiments show it can detect as more faults as possible with fewer test pairs.
本文还提出了一种面向最小相关度多捕获结构的测试向量生成算法。
A new test vector generation method for Multi-capture structure is presented to generate more efficient vectors.
实验结果表明，该周期化方法是一种行之有效的测试向量转换方法。
Experimental results show that this approach is efficient and automated in test vector translation.
对于确定的测试向量集，用该方法构造的扫描链能使电路总的测试时间最少。
For a fixed set of test vectors, the overall test time can be minimized using the scan chain constructed with this method.
对于确定的测试向量集，用该方法构造的扫描链能使电路总的测试时间最少。
For a fixed set of test vectors, the overall test time can be minimized using the scan chain constructed by this method.
通过抽象，电路可以规范为行为集，并代替电路本身进行功能测试向量的生成。
Circuits described are modeled to behavior sets after abstraction, and can be replaced by their behavior sets during functional test vector generation procedures.
压缩时，先对测试向量集进行差分运算，然后采用CPRL码编码差分向量序列。
During compression, it generates difference vectors from test data and then encoding the vectors with CPRL codes.
通过两级遍历，自动生成系统测试向量，并且达到所提的系统测试覆盖率的要求。
Through two levels traverse, generate test cases automatically and satisfy the coverage criteria stated in this paper.
结合一个实际电路，研究了一种可把数字电路故障定位到器件级的测试向量生成算法。
This paper studies a test vector generation algorithm for digital circuits which can locate the component faults.
兼容于BSDL和EDIF文件格式的自动测试向量生成软件可实现多种扫描测试功能。
The automatic testing software which is compatible with BSDL files and EDIF files can complete multiple boundary scan test tasks.
该算法将测试向量空间映射到混沌空间并采用混沌搜索来寻找一对符合要求的测试向量对。
The algorithm maps test vector space to the chaotic space and USES chaotic search to find out the suitable testing pairs.
BIST控制器不仅可以执行传统的存储器测试算法，而且可以生成用于逻辑模块的测试向量。
The BIST controller can not only perform traditional memory test algorithms but also generates test patterns required for the logic part.
实验表明，对于输入端较多的电路，该方法生成的测试向量序列长度极大的减少，硬件开销也较小。
The experimental results show that for the circuits having many inputs, the length of test vectors generated by this method is much shorter and the hardware cost is smaller.
因此，如何快速产生准确的功能测试向量就成为降低产品测试成本和缩短产品上市时间的关键因素。
Therefore, how to quickly generate accurate functional test pattern has turned to be the important factor in lower production test cost and shorter time to market.
当某个子扫描链的测试向量需要更新且又不需要移出其测试响应时，其测试向量由可控LFSR产生。
The test vectors of some sub-scan chains generate by controllable LFSR when these chains only need to update test vector and do not need to shift out test responses.
对于这些测试向量对，通过SPICE软件模拟了故障电路和无故障电路在测试向量对作用下的动态电流。
SPICE experiments were done to simulate the dynamic currents of both the fault circuits and fault free circuits under the function of testing pairs.
为进一步降低测试功耗及测试应用时间，提出一种基于扫描链阻塞技术且针对非相容测试向量的压缩方法。
For the test application time can be reduced effectively, this paper proposes an approach based on scan chain disabling technique, in view of incompatible test vector compression method.
研究如何有效地压缩向量对测试集与通常的测试向量压缩一样，意义十分重要，但目前人们对此研究得较少。
Obviously, it is significant to find out effective ways to compress the set of pairs of test vectors, as well as conventional test vectors compression.
提出了评价测试向量集及其生成算法的系统化方法，运用该方法对现有的并行测试生成算法进行了深入分析。
A new systematic method for evaluating interconnect testing algorithms is presented. Using this method, the parallel testing algorithms proposed in the literature are analyZed in detail.
这种方法利用确定性测试向量中存在的大量不确定位（X位），采用对测试向量进行扫描切片划分和兼容赋值的思想。
Thismethod exploits the large number of don't care bits (X) in test cubes and analyzescompatible relationships among scan slices.
为了减少测试向量的存储需求，提出一种基于扭环计数器作为测试向量产生器的横向和竖向测试数据压缩的BIST方案。
In order to reduce the storage requirements for the test patterns, a vertical and horizontal test data compression BIST scheme based on the test pattern generation of twisted-ring counter is proposed.
针对数字系统仿真、故障诊断中对测试向量的特殊要求，利用VB 5 0开发出了拖拽鼠标快速生成测试向量的软件包。
To satisfy specialized demands of test vector in digital circuit simulation and fault diagnosis, we develop a software package"Dragging Mouse to Generate Test Vector"by VB5.0.
本文基于SAPPHIRE集成电路测试系统，介绍了自行开发的从VCD测试向量到STIL测试向量的转换软件及流程。
This paper introduces the special software and flow converted from VCD test vector to STIL test vector, which is based of SAPPHIRE SOC test System.
该算法利用改进FAN算法的反向蕴涵部分激活故障并将测试向量空间映射到混沌空间，采用混沌搜索来确定未确定的测试向量位。
The algorithm used backward implication in improved FAN algorithm to activate fault and mapped test vector space to the chaotic space, adopted chaotic search to find out the suitable testing pairs.
本文给出了一种新型的瞬态电流测试BIST测试生成器设计方案，该设计可以产生所需要的测试向量对，同时具有硬件开销小的优点。
This article gives a new BIST test generator design for transient current testing, this design not only produces needed test vector pairs but also has an advantage of low hardware overheads.
本文设计了一种基于堆栈效应的漏电流模拟器，并提出了通过该模拟器，利用测试向量中特有的不确定位以优化测试中静态功耗的方法。
Using the simulator, we give a method based on the don t care bits in the test vectors to optimize the static test power.
本文设计了一种基于堆栈效应的漏电流模拟器，并提出了通过该模拟器，利用测试向量中特有的不确定位以优化测试中静态功耗的方法。
Using the simulator, we give a method based on the don t care bits in the test vectors to optimize the static test power.
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