流水线ADC的模块有采样保持电路、乘法数模转换器、子ADC、数字校正电路、时钟产生电路和时间对齐电路。
The whole circuit consists of Sample and Hold Circuit, the Multiplicative A/D Converter, the Sub-ADC, the Digital Calibration Circuit, the Clock Generator and the Time Synchronizer.
此系统由程序接触器、自制的时刻比对自动转换器、时间间隔计数器和数字打印机组成。
The system consists of a programme contactor, a automatic transfer device which was completely designed and built by ourselves, a time interval counter and a digital recoder.
作为全数字锁相环的关键模块，时间数字转换器的性能在一定程度决定其性能的好坏。
As the core module of all-digital PLL, time-to-digital converter determines its performance largely.
可是，这种信号发生器的上限频率的提高受存储器的读取时间和数模转换器的转换速度的限制。为了提高数字法函数信号发生器的上限频率，我们提出了用分布存储式数字法生成函数信号。
However, extending the upper frequency of such function signal generator is limited by the read-out time of the memory and the conversion rate of the digital-to-analog converter.
可是，这种信号发生器的上限频率的提高受存储器的读取时间和数模转换器的转换速度的限制。为了提高数字法函数信号发生器的上限频率，我们提出了用分布存储式数字法生成函数信号。
However, extending the upper frequency of such function signal generator is limited by the read-out time of the memory and the conversion rate of the digital-to-analog converter.
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