本文分析了常用对称密码算法DES、3des和AES的可重构性，利用流水线、并行处理和可重构技术，提出了一种可重构体系结构。
In this paper, based on the analysis about the reconfiguration of the DES, 3des and AES, we propose a reconfigurable architecture, which combines reconfiguration technology with pipeline, par.
软件流水和循环展开是开发循环并行性的两种重要编译优化技术。
Software pipelining and loop unroll are two kinds of important optimized compile technique to develop loop parallelism.
本文的设计着重从多个层次利用并行处理技术来提高环路滤波的速度，包括流水线设计、数据流驱动控制策略以及算法并行性设计。
Our design emphasizes on using parallel processing technology from multi-level to improve speed, including pipelining design, data-flow drive strategy and algorithmic parallelism design.
本文设计的FFT处理器采用流水线和并行处理技术，在64个时钟周期完成64点复数定点FFT运算，可以满足OFDM系统的需要。
The FFT processer adopts the pipeline and parallel technology and can complete 64 points FFT computation in 64 clocks. It is able to meet the need of OFDM system.
该文从消除时钟信号冗余跳变而致的无效功耗的要求出发，提出了应用并行技术和流水线技术，实现基于RTL级的双边沿触发计数器的设计。
To erase the bootless power dissipation of the redundant leap of the clock, this paper proposes the RTL design of double edge triggered counter using parallelism and pipeline technique.
数字信号处理(dsp)具有并行的硬件乘法器、流水线结构以及快速的片内存储器等资源，其技术广泛地应用于数字信号处理的各个领域。
DSP technologies have applied in every field of digital signal processing because of its parallel multiplier, pipeline structure and fast On-Chip memory.
FPGA在分布式计算、并行处理、流水线结构上有独特的优势，自然成为设计软件无线电系统的首选技术之一。
FPGA has become the first choice for designing the software radio system because of its unique advantages in distributed computing, parallel processing and pipelining.
该技术与传统流水技术的不同在于，能从复杂的循环结构中发掘流水并行。
The technique exploits pipelining from complex loop structures, which distinguishes itself from traditional pipelining techniques.
软件流水是一种开发循环程序指令级并行性的技术，它通过并行执行连续的多个迭代来加快循环的执行速度。
Software pipelining is a loop scheduling technique which extracts instruction level parallelism by overlapping the execution of several consecutive iterations.
基于流水线技术和并行技术的硬件设计保证了该算法的实时实现。
Based on pipeline and parallelism technology, the processor can run in real-time.
同时采用并行流水线技术，提高了解码的速度。
The parallel pipeline is also adopted to enhance the decode efficiency.
同时采用并行流水线技术，提高了解码的速度。
The parallel pipeline is also adopted to enhance the decode efficiency.
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