其控制主体采用DSP（数字信号处理器）结合CPLD（复杂可编程逻辑器件）。
The control mainframe of the robot is composed of a Digital Signal Processor(DSP) and a Complex Programmable Logic Device(CPLD).
基于EPP协议的特点，应用复杂可编程逻辑器件(CPLD)开发了移位寄存器输出接口。
Based on the properties of Enhanced Parallel Port (EPP), an interface of shift register output has been developed using Complex Programmable Logic Device (CPLD).
介绍了一种利用复杂可编程逻辑器件（CPLD）设计CMOS有源像素图像传感器驱动电路的方法。
A method for designing driving circuit of CMOS active-pixel image sensor by means of the complex programmable logic device (CPLD)was introduced .
介绍了在三相三开关高功率因数变换器中应用复杂可编程逻辑器件(CPLD)实现逻辑控制部分的方案。
This paper introduces a scheme in which a complex programmable logic device (CPLD) is used in the three phase three pole switch high rating factor convertor to realize logic control.
用数字信号处理器(dsp)和复杂可编程逻辑器件(CPLD)设计了IGBT感应加热电源控制系统。
The control system of IGBT induction heating power supply is designed based on DSP (digital signal processor) and CPLD (complex programmable logic device).
介绍利用复杂可编程逻辑器件CPLD和直接数字合成专用电路dds，设计雷达信号回波模拟器的硬件系统。
Introduce how to design hardware system structure of radar signal echo simulator by using CPLD and DDS.
本系统采用了以DSP、MCU（微控制器）、CPLD（复杂可编程逻辑器件）为核心的系统硬件结构以及数字视频技术。
The system uses DSP, MCU (Microcontrol Unit) and CPLD (Complex Programable Logic Device) as the core of the system hardware and uses digital video technology.
针对如何用复杂可编程逻辑器件实现4dps K信号的解调，提出了一种基于CPLD的4dps K信号解调器设计方案。
This article presents a design scheme of 2-digitization 4dpsk demodulator, which aim at how to implement 4dpsk signal demodulate with CPLD.
提出了一种以复杂可编程逻辑器件（CPLD）和锁相环技术为核心的新型通用数字触发器，对其硬件电路和软件设计进行了详细分析。
To aim at the defect of the simulate trigger and the digital trigger with microcomputer, a new universal digital trigger based on CPLD and PLL is introduced.
介绍一种针对正、余弦旋转变压器数字转换器（RDC）模块，用复杂可编程逻辑器件（CPLD）技术实现伺服轴角编码电路设计的方案。
This paper introduces the technology scheme to design radar servo shaft encoder circuit by using CPLD on the rotary transformer and RDC module.
根据单元级联多电平变换器拓扑结构及其脉宽调制技术的特点，以数字信号处理器和复杂可编程逻辑器件为核心，设计了多电平变换器的控制器。
On the basis of topology of cascaded multilevel convertor and its PWM technique, designed the controller of multilevel convertor at the core of DSP and CPLD.
测试系统中采用了以数字信号处理器为核心，以复杂可编程逻辑器件为外围电路，来控制执行部件和测试与接收由外部返回的数字信号、模拟信号和开关信号。
Testing system, in which DSP is the part of core and CPLD is as peripheral circuit, controls operation parts, and test or incept the digital signal, analog signals and switch signals from exterior.
介绍了新型通信控制器的硬件设计，着重描述了通信接口部分，用复杂可编程逻辑器件CPLD解决了CAN 控制器芯片SJA 1000与AT 91RM 9200之间的时序逻辑问题。
The hardware structure is introduced, emphatically the communication interface circuit. The time sequence logic problem between CAN controller chip SJA1000 and AT91RM9200 is solved using the CPLD.
采用复杂可编程逻辑芯片CPLD和先进的EDA设计软件，实现了高性能的三相全控桥晶闸管的数字触发器。
A high performance 3-phases full controlled thyristor trigger is achieved by the complex programmable logic devices (CPLD) and the advanced EDA software.
对于采用可编程逻辑控制器(PLC)实现的复杂离散事件控制系统(DECS)，现有设计方法在效率和易用性等方面存在不足。
Existing design methods for discrete event control system (DECS) implemented with programmable logical controller (PLC) have disadvantages in efficiency and ease of use.
对于采用可编程逻辑控制器(PLC)实现的复杂离散事件控制系统(DECS)，现有设计方法在效率和易用性等方面存在不足。
Existing design methods for discrete event control system (DECS) implemented with programmable logical controller (PLC) have disadvantages in efficiency and ease of use.
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