而集成电路的后端设计包括了版图设计和验证，它们不在本论文的讨论范围之内。
The back-end design includes layout design and verification, but they will not be discussed in this paper.
课题着重对这两个模块的电路结构以及版图结构进行了深入的研究和分析，并采用SPICE工具进行了模拟验证。
The paper has an emphatical discussion on the study and analysis of the circuit structure and layout structure of these two modules, and makes a lot of SPICE simulation and verification.
介绍了VLSI版图验证中电阻提取的基本原理和主要方法，给出了一种新颖的基于边界元法的电阻提取算法。
The basic theory of resistance extraction in VLSI layout verification is described. A novel resistance extractor based on the boundary element method is presented.
最后，深入讨论模拟部分版图设计相关问题，并完成了版图设计和验证工作。
Finally, the problems about layout design in analog part are discussed, and layout design and verification are accomplished.
最后利用FPGA平台实现了BIST的功能和时序验证，并通过综合、静态时序分析、自动布局布线实现了BIST系统的版图设计。
Finally USES FPGA platform for BIST functions and timing verification, and through design compiler, static timing analysis, automatic placing and routing to achieve a BIST system layout.
最后利用FPGA平台实现了BIST的功能和时序验证，并通过综合、静态时序分析、自动布局布线实现了BIST系统的版图设计。
Finally USES FPGA platform for BIST functions and timing verification, and through design compiler, static timing analysis, automatic placing and routing to achieve a BIST system layout.
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