Learn how to improve your design's timing and performance with the Xilinx Constraints Editor.
通过讲师生动的讲解，实时了解如何缩短开发时间，并提高设计性能。
In this series, I work specifically with the Xilinx ML403 EDK, which is a high-end development platform.
在本系列中，我将特别介绍Xilinx ML 403EDK，它是一种高端开发平台。
This is based on the Xilinx Spartan3 Adder, Verilog language use, EDA newcomer has some reference value.
这是个基于XilinxSpartan3的加法器，利用Verilog语言编写，对于EDA初学者来说有一定的参考价值。
We expect FPGAs from Xilinx along with graphics from NVIDIA emerging as a significant beneficiary of that trend.
我们预计赛灵思的FPGA和NVIDIA的图形将成为这一趋势的重要受益者。
Note that you can obtain evaluation versions of most of the commercial cores from Xilinx, but they are quite limited.
请注意，可以从Xilinx得到多数商业核心的评估版本，但是它们的功能非常有限。
Note that there are several other possible buses in a Xilinx design; other buses can be added from the list in the upper right of this dialog.
请注意：在Xilinx的设计中还可能有其他几个总线；可以从此对话框右上角的列表中添加其他总线。
You're now asked to select from a list of standard target platforms; this version of the EDK supports eight different target boards from Xilinx.
现在将要求您在一些标准目标平台中做出选择；此版本的EDK支持来自 Xilinx 的8 种不同的目标板。
When I first opened the shipping container, I thought Xilinx had sent me two kits, since the package is comprised of two superficially identical glossy boxes.
当我第一次打开货运包装时，我以为Xilinx给我送来了两个工具包，因为包裹中有两个表面上一模一样的盒子。
Based on a detailed study of the FPGA, using distributed algorithm FIR digital filter method and the principle, and through the Xilinx ISE under the Modelsim simulation.
详细研究了基于FPGA、采用分布式算法实现FIR数字滤波器的原理和方法，并通过XilinxISE在Models im下进行了仿真。
You could also explore free third-party cores from sources such as opencores (see Resources), but some adaptation will definitely be necessary to connect these cores to Xilinx bus IP.
还可以从opencores这类来源寻求免费的第三方核心(请参阅参考资料)，但要把这些核心连接到Xilinx总线IP，肯定需要做些适配工作。
You could also explore free third-party cores from sources such as opencores (see Resources), but some adaptation will definitely be necessary to connect these cores to Xilinx bus IP.
还可以从opencores这类来源寻求免费的第三方核心(请参阅参考资料)，但要把这些核心连接到Xilinx总线IP，肯定需要做些适配工作。
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